From 415c5ff41291d0a93c42ad5fc66b404321a9e7dc Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Thu, 18 Aug 2011 13:00:48 +0000 Subject: [PATCH] Add intrinsics for SETEV, GETED, GETET. llvm-svn: 137938 --- include/llvm/IntrinsicsXCore.td | 4 ++++ lib/Target/XCore/XCoreInstrInfo.td | 28 ++++++++++++++++++++------- test/CodeGen/XCore/misc-intrinsics.ll | 18 +++++++++++++++++ test/CodeGen/XCore/resources.ll | 9 +++++++++ 4 files changed, 52 insertions(+), 7 deletions(-) diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td index 93f555da0e6..28b5478a247 100644 --- a/include/llvm/IntrinsicsXCore.td +++ b/include/llvm/IntrinsicsXCore.td @@ -24,6 +24,8 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; + def int_xcore_geted : Intrinsic<[llvm_i32_ty],[]>; + def int_xcore_getet : Intrinsic<[llvm_i32_ty],[]>; def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>; def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>; @@ -66,6 +68,8 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". [NoCapture<0>]>; def int_xcore_setv : Intrinsic<[],[llvm_anyptr_ty, llvm_ptr_ty], [NoCapture<0>]>; + def int_xcore_setev : Intrinsic<[],[llvm_anyptr_ty, llvm_ptr_ty], + [NoCapture<0>]>; def int_xcore_eeu : Intrinsic<[],[llvm_anyptr_ty], [NoCapture<0>]>; def int_xcore_setclk : Intrinsic<[],[llvm_anyptr_ty, llvm_anyptr_ty], [NoCapture<0>, NoCapture<1>]>; diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index d310a510489..a1ec8aad87b 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -995,10 +995,15 @@ def FREER_1r : _F1R<(outs), (ins GRRegs:$r), "freer res[$r]", [(int_xcore_freer GRRegs:$r)]>; -let Uses=[R11] in +let Uses=[R11] in { def SETV_1r : _F1R<(outs), (ins GRRegs:$r), - "setv res[$r], r11", - [(int_xcore_setv GRRegs:$r, R11)]>; + "setv res[$r], r11", + [(int_xcore_setv GRRegs:$r, R11)]>; + +def SETEV_1r : _F1R<(outs), (ins GRRegs:$r), + "setev res[$r], r11", + [(int_xcore_setev GRRegs:$r, R11)]>; +} def EEU_1r : _F1R<(outs), (ins GRRegs:$r), "eeu res[$r]", @@ -1006,15 +1011,24 @@ def EEU_1r : _F1R<(outs), (ins GRRegs:$r), // Zero operand short // TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, -// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, +// stet, getkep, getksp, setkep, getid, kret, dcall, dret, // dentsp, drestsp def CLRE_0R : _F0R<(outs), (ins), "clre", [(int_xcore_clre)]>; -let Defs = [R11] in +let Defs = [R11] in { def GETID_0R : _F0R<(outs), (ins), - "get r11, id", - [(set R11, (int_xcore_getid))]>; + "get r11, id", + [(set R11, (int_xcore_getid))]>; + +def GETED_0R : _F0R<(outs), (ins), + "get r11, ed", + [(set R11, (int_xcore_geted))]>; + +def GETET_0R : _F0R<(outs), (ins), + "get r11, et", + [(set R11, (int_xcore_getet))]>; +} def SSYNC_0r : _F0R<(outs), (ins), "ssync", diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll index 458f23f28f0..6d39d77929a 100644 --- a/test/CodeGen/XCore/misc-intrinsics.ll +++ b/test/CodeGen/XCore/misc-intrinsics.ll @@ -6,6 +6,8 @@ declare i32 @llvm.xcore.crc32(i32, i32, i32) declare %0 @llvm.xcore.crc8(i32, i32, i32) declare i32 @llvm.xcore.zext(i32, i32) declare i32 @llvm.xcore.sext(i32, i32) +declare i32 @llvm.xcore.geted() +declare i32 @llvm.xcore.getet() define i32 @bitrev(i32 %val) { ; CHECK: bitrev: @@ -55,3 +57,19 @@ define i32 @sexti(i32 %a) { %result = call i32 @llvm.xcore.sext(i32 %a, i32 4) ret i32 %result } + +define i32 @geted() { +; CHECK: geted: +; CHECK: get r11, ed +; CHECK-NEXT: mov r0, r11 + %result = call i32 @llvm.xcore.geted() + ret i32 %result +} + +define i32 @getet() { +; CHECK: getet: +; CHECK: get r11, et +; CHECK-NEXT: mov r0, r11 + %result = call i32 @llvm.xcore.getet() + ret i32 %result +} diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll index f0f528f37d8..8f00fed160b 100644 --- a/test/CodeGen/XCore/resources.ll +++ b/test/CodeGen/XCore/resources.ll @@ -20,6 +20,7 @@ declare i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r) declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) declare void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) +declare void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p) declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r) declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) @@ -175,6 +176,14 @@ define void @setv(i8 addrspace(1)* %r, i8* %p) { ret void } +define void @setev(i8 addrspace(1)* %r, i8* %p) { +; CHECK: setev: +; CHECK: mov r11, r1 +; CHECK-NEXT: setev res[r0], r11 + call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p) + ret void +} + define void @eeu(i8 addrspace(1)* %r) { ; CHECK: eeu: ; CHECK: eeu res[r0]