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[X86] Add 64-bit int to float/double conversion with AVX to X86FastISel::X86SelectSIToFP
Summary: [X86] Teach fast isel to handle i64 sitofp with AVX. For some reason we only handled i32 sitofp with AVX. But with SSE only we support i64 so we should do the same with AVX. Also add i686 command lines for the 32-bit tests. 64-bit tests are in a separate file to avoid a fast-isel abort failure in 32-bit mode. Reviewers: RKSimon, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39450 llvm-svn: 317102
This commit is contained in:
Craig Topper
parent
80050c8c6e
commit
417304621b
@ -2410,7 +2410,8 @@ bool X86FastISel::X86SelectSIToFP(const Instruction *I) {
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if (!Subtarget->hasAVX())
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return false;
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if (!I->getOperand(0)->getType()->isIntegerTy(32))
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Type *InTy = I->getOperand(0)->getType();
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if (!InTy->isIntegerTy(32) && !InTy->isIntegerTy(64))
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return false;
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// Select integer to float/double conversion.
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@ -2423,11 +2424,11 @@ bool X86FastISel::X86SelectSIToFP(const Instruction *I) {
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if (I->getType()->isDoubleTy()) {
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// sitofp int -> double
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Opcode = X86::VCVTSI2SDrr;
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Opcode = InTy->isIntegerTy(64) ? X86::VCVTSI2SD64rr : X86::VCVTSI2SDrr;
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RC = &X86::FR64RegClass;
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} else if (I->getType()->isFloatTy()) {
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// sitofp int -> float
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Opcode = X86::VCVTSI2SSrr;
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Opcode = InTy->isIntegerTy(64) ? X86::VCVTSI2SS64rr : X86::VCVTSI2SSrr;
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RC = &X86::FR32RegClass;
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} else
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return false;
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66
test/CodeGen/X86/fast-isel-int-float-conversion-x86-64.ll
Normal file
66
test/CodeGen/X86/fast-isel-int-float-conversion-x86-64.ll
Normal file
@ -0,0 +1,66 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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define double @long_to_double_rr(i64 %a) {
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; SSE2-LABEL: long_to_double_rr:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: cvtsi2sdq %rdi, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_double_rr:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sitofp i64 %a to double
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ret double %0
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}
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define double @long_to_double_rm(i64* %a) {
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; SSE2-LABEL: long_to_double_rm:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: cvtsi2sdq (%rdi), %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_double_rm:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2sdq (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = load i64, i64* %a
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define float @long_to_float_rr(i64 %a) {
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; SSE2-LABEL: long_to_float_rr:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: cvtsi2ssq %rdi, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_float_rr:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = sitofp i64 %a to float
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ret float %0
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}
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define float @long_to_float_rm(i64* %a) {
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; SSE2-LABEL: long_to_float_rm:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: cvtsi2ssq (%rdi), %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: long_to_float_rm:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2ssq (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%0 = load i64, i64* %a
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX
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; RUN: llc -mtriple=i686-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=SSE2_X86
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; RUN: llc -mtriple=i686-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=AVX_X86
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define double @int_to_double_rr(i32 %a) {
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@ -13,6 +15,39 @@ define double @int_to_double_rr(i32 %a) {
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; SSE2_X86-LABEL: int_to_double_rr:
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; SSE2_X86: # BB#0: # %entry
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; SSE2_X86-NEXT: pushl %ebp
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; SSE2_X86-NEXT: .cfi_def_cfa_offset 8
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; SSE2_X86-NEXT: .cfi_offset %ebp, -8
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; SSE2_X86-NEXT: movl %esp, %ebp
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; SSE2_X86-NEXT: .cfi_def_cfa_register %ebp
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; SSE2_X86-NEXT: andl $-8, %esp
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; SSE2_X86-NEXT: subl $8, %esp
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; SSE2_X86-NEXT: movl 8(%ebp), %eax
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; SSE2_X86-NEXT: cvtsi2sdl %eax, %xmm0
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; SSE2_X86-NEXT: movsd %xmm0, (%esp)
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; SSE2_X86-NEXT: fldl (%esp)
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; SSE2_X86-NEXT: movl %ebp, %esp
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; SSE2_X86-NEXT: popl %ebp
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; SSE2_X86-NEXT: retl
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;
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; AVX_X86-LABEL: int_to_double_rr:
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; AVX_X86: # BB#0: # %entry
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; AVX_X86-NEXT: pushl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: .cfi_offset %ebp, -8
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; AVX_X86-NEXT: movl %esp, %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_register %ebp
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; AVX_X86-NEXT: andl $-8, %esp
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; AVX_X86-NEXT: subl $8, %esp
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; AVX_X86-NEXT: vcvtsi2sdl 8(%ebp), %xmm0, %xmm0
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; AVX_X86-NEXT: vmovsd %xmm0, (%esp)
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; AVX_X86-NEXT: fldl (%esp)
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; AVX_X86-NEXT: movl %ebp, %esp
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; AVX_X86-NEXT: popl %ebp
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; AVX_X86-NEXT: retl
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entry:
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%0 = sitofp i32 %a to double
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ret double %0
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@ -28,6 +63,40 @@ define double @int_to_double_rm(i32* %a) {
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2sdl (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; SSE2_X86-LABEL: int_to_double_rm:
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; SSE2_X86: # BB#0: # %entry
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; SSE2_X86-NEXT: pushl %ebp
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; SSE2_X86-NEXT: .cfi_def_cfa_offset 8
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; SSE2_X86-NEXT: .cfi_offset %ebp, -8
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; SSE2_X86-NEXT: movl %esp, %ebp
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; SSE2_X86-NEXT: .cfi_def_cfa_register %ebp
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; SSE2_X86-NEXT: andl $-8, %esp
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; SSE2_X86-NEXT: subl $8, %esp
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; SSE2_X86-NEXT: movl 8(%ebp), %eax
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; SSE2_X86-NEXT: cvtsi2sdl (%eax), %xmm0
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; SSE2_X86-NEXT: movsd %xmm0, (%esp)
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; SSE2_X86-NEXT: fldl (%esp)
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; SSE2_X86-NEXT: movl %ebp, %esp
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; SSE2_X86-NEXT: popl %ebp
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; SSE2_X86-NEXT: retl
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;
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; AVX_X86-LABEL: int_to_double_rm:
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; AVX_X86: # BB#0: # %entry
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; AVX_X86-NEXT: pushl %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: .cfi_offset %ebp, -8
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; AVX_X86-NEXT: movl %esp, %ebp
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; AVX_X86-NEXT: .cfi_def_cfa_register %ebp
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; AVX_X86-NEXT: andl $-8, %esp
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; AVX_X86-NEXT: subl $8, %esp
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; AVX_X86-NEXT: movl 8(%ebp), %eax
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; AVX_X86-NEXT: vcvtsi2sdl (%eax), %xmm0, %xmm0
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; AVX_X86-NEXT: vmovsd %xmm0, (%esp)
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; AVX_X86-NEXT: fldl (%esp)
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; AVX_X86-NEXT: movl %ebp, %esp
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; AVX_X86-NEXT: popl %ebp
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; AVX_X86-NEXT: retl
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entry:
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%0 = load i32, i32* %a
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%1 = sitofp i32 %0 to double
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@ -44,6 +113,27 @@ define float @int_to_float_rr(i32 %a) {
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; SSE2_X86-LABEL: int_to_float_rr:
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; SSE2_X86: # BB#0: # %entry
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; SSE2_X86-NEXT: pushl %eax
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; SSE2_X86-NEXT: .cfi_def_cfa_offset 8
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; SSE2_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE2_X86-NEXT: cvtsi2ssl %eax, %xmm0
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; SSE2_X86-NEXT: movss %xmm0, (%esp)
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; SSE2_X86-NEXT: flds (%esp)
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; SSE2_X86-NEXT: popl %eax
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; SSE2_X86-NEXT: retl
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;
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; AVX_X86-LABEL: int_to_float_rr:
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; AVX_X86: # BB#0: # %entry
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; AVX_X86-NEXT: pushl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: vcvtsi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0
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; AVX_X86-NEXT: vmovss %xmm0, (%esp)
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; AVX_X86-NEXT: flds (%esp)
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; AVX_X86-NEXT: popl %eax
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; AVX_X86-NEXT: retl
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entry:
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%0 = sitofp i32 %a to float
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ret float %0
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@ -59,6 +149,28 @@ define float @int_to_float_rm(i32* %a) {
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vcvtsi2ssl (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; SSE2_X86-LABEL: int_to_float_rm:
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; SSE2_X86: # BB#0: # %entry
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; SSE2_X86-NEXT: pushl %eax
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; SSE2_X86-NEXT: .cfi_def_cfa_offset 8
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; SSE2_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE2_X86-NEXT: cvtsi2ssl (%eax), %xmm0
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; SSE2_X86-NEXT: movss %xmm0, (%esp)
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; SSE2_X86-NEXT: flds (%esp)
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; SSE2_X86-NEXT: popl %eax
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; SSE2_X86-NEXT: retl
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;
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; AVX_X86-LABEL: int_to_float_rm:
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; AVX_X86: # BB#0: # %entry
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; AVX_X86-NEXT: pushl %eax
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; AVX_X86-NEXT: .cfi_def_cfa_offset 8
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; AVX_X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; AVX_X86-NEXT: vcvtsi2ssl (%eax), %xmm0, %xmm0
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; AVX_X86-NEXT: vmovss %xmm0, (%esp)
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; AVX_X86-NEXT: flds (%esp)
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; AVX_X86-NEXT: popl %eax
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; AVX_X86-NEXT: retl
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entry:
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%0 = load i32, i32* %a
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%1 = sitofp i32 %0 to float
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