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[Hexagon] Rename TypeCOMPOUND to TypeCJ

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llvm-svn: 293894
This commit is contained in:
Krzysztof Parzyszek 2017-02-02 15:03:30 +00:00
parent d4909b474b
commit 417b2207b8
8 changed files with 15 additions and 16 deletions
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2
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
View File

@ -332,7 +332,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
// follow the duplex model, so the register values in the MCInst are
// incorrect. If the instruction is a compound, loop through the
// operands and change registers appropriately.
if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCOMPOUND) {
if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCJ) {
for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) {
if (i->isReg()) {
unsigned reg = i->getReg() - Hexagon::R0;

8
lib/Target/Hexagon/HexagonInstrFormatsV4.td
View File

@ -17,10 +17,10 @@
// *** Must match BaseInfo.h ***
//----------------------------------------------------------------------------//
def TypeV4LDST : IType<9>;
def TypeV4LDST : IType<9>;
def TypeNV : IType<10>;
def TypeDUPLEX : IType<11>;
def TypeCOMPOUND : IType<12>;
def TypeCJ : IType<12>;
def TypePREFIX : IType<30>;
// Duplex Instruction Class Declaration
@ -150,11 +150,11 @@ class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
: InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>,
: InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>,
OpcodeHexagon;
class CJInst_JMPSET<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
: InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>,
: InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCJ>,
OpcodeHexagon;

2
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1713,7 +1713,7 @@ bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
// Return true if the instruction is a compund branch instruction.
bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
return (getType(MI) == HexagonII::TypeCOMPOUND && MI.isBranch());
return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
}
bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const {

8
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -3056,7 +3056,7 @@ class CJInst_tstbit_R0<string px, bit np, string tnt>
: InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
""#px#" = tstbit($Rs, #0); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<11> r9_2;
@ -3102,7 +3102,7 @@ class CJInst_RR<string px, string op, bit np, string tnt>
: InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
""#px#" = cmp."#op#"($Rs, $Rt); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<4> Rt;
bits<11> r9_2;
@ -3156,7 +3156,7 @@ class CJInst_RU5<string px, string op, bit np, string tnt>
: InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2),
""#px#" = cmp."#op#"($Rs, #$U5); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<5> U5;
bits<11> r9_2;
@ -3211,7 +3211,7 @@ class CJInst_Rn1<string px, string op, bit np, string tnt>
: InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2),
""#px#" = cmp."#op#"($Rs,#$n1); if ("
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
bits<4> Rs;
bits<11> r9_2;

3
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
View File

@ -524,8 +524,7 @@ public:
bool Relaxable = false;
// Branches and loop-setup insns are handled as necessary by relaxation.
if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
HexagonII::TypeCOMPOUND &&
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
MCID.isBranch()) ||
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
MCID.isBranch()) ||

2
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
View File

@ -44,7 +44,7 @@ namespace HexagonII {
TypeV4LDST = 9,
TypeNV = 10,
TypeDUPLEX = 11,
TypeCOMPOUND = 12,
TypeCJ = 12,
TypeCVI_FIRST = 13,
TypeCVI_VA = TypeCVI_FIRST,
TypeCVI_VA_DV = 14,

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
View File

@ -126,7 +126,7 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(
" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
"\n");
if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCJ) {
for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
if (HMB.getOperand(i).isReg()) {
unsigned Reg =

4
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
View File

@ -438,7 +438,7 @@ bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
MCInst const &MCI) {
return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
return getType(MCII, MCI) == HexagonII::TypeCJ;
}
bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
@ -470,7 +470,7 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
return true;
// Branch insns are handled as necessary by relaxation.
if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))