mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 19:52:54 +01:00
Teach x86 fast-isel to use AVX opcodes for vector stores when AVX is enabled.
llvm-svn: 186496
This commit is contained in:
parent
ade122d371
commit
418481460c
@ -264,24 +264,24 @@ X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg,
|
|||||||
break;
|
break;
|
||||||
case MVT::v4f32:
|
case MVT::v4f32:
|
||||||
if (Aligned)
|
if (Aligned)
|
||||||
Opc = X86::MOVAPSmr;
|
Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
|
||||||
else
|
else
|
||||||
Opc = X86::MOVUPSmr;
|
Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
|
||||||
break;
|
break;
|
||||||
case MVT::v2f64:
|
case MVT::v2f64:
|
||||||
if (Aligned)
|
if (Aligned)
|
||||||
Opc = X86::MOVAPSmr;
|
Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
|
||||||
else
|
else
|
||||||
Opc = X86::MOVUPSmr;
|
Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
|
||||||
break;
|
break;
|
||||||
case MVT::v4i32:
|
case MVT::v4i32:
|
||||||
case MVT::v2i64:
|
case MVT::v2i64:
|
||||||
case MVT::v8i16:
|
case MVT::v8i16:
|
||||||
case MVT::v16i8:
|
case MVT::v16i8:
|
||||||
if (Aligned)
|
if (Aligned)
|
||||||
Opc = X86::MOVDQAmr;
|
Opc = Subtarget->hasAVX() ? X86::VMOVDQAmr : X86::MOVDQAmr;
|
||||||
else
|
else
|
||||||
Opc = X86::MOVDQUmr;
|
Opc = Subtarget->hasAVX() ? X86::VMOVDQUmr : X86::MOVDQUmr;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user