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[Hexagon] Fix an incorrect assertion in HexagonConstExtenders
llvm-svn: 323548
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3f75e2a143
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@ -999,15 +999,19 @@ unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const {
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return 0;
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}
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// Return the allowable deviation from the current value of Rb which the
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// Return the allowable deviation from the current value of Rb (i.e. the
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// range of values that can be added to the current value) which the
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// instruction MI can accommodate.
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// The instruction MI is a user of register Rb, which is defined via an
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// extender. It may be possible for MI to be tweaked to work for a register
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// defined with a slightly different value. For example
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// ... = L2_loadrub_io Rb, 0
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// ... = L2_loadrub_io Rb, 1
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// can be modifed to be
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// ... = L2_loadrub_io Rb', 1
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// if Rb' = Rb-1.
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// ... = L2_loadrub_io Rb', 0
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// if Rb' = Rb+1.
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// The range for Rb would be [Min+1, Max+1], where [Min, Max] is a range
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// for L2_loadrub with offset 0. That means that Rb could be replaced with
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// Rc, where Rc-Rb belongs to [Min+1, Max+1].
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OffsetRange HCE::getOffsetRange(Register Rb, const MachineInstr &MI) const {
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unsigned Opc = MI.getOpcode();
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// Instructions that are constant-extended may be replaced with something
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@ -1618,7 +1622,7 @@ bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
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assert(IdxOpc == Hexagon::A2_addi);
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// Clamp Diff to the 16 bit range.
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int32_t D = isInt<16>(Diff) ? Diff : (Diff > 32767 ? 32767 : -32767);
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int32_t D = isInt<16>(Diff) ? Diff : (Diff > 0 ? 32767 : -32768);
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BuildMI(MBB, At, dl, HII->get(IdxOpc))
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.add(MI.getOperand(0))
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.add(MachineOperand(ExtR))
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@ -1626,11 +1630,13 @@ bool HCE::replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
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Diff -= D;
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#ifndef NDEBUG
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// Make sure the output is within allowable range for uses.
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// "Diff" is a difference in the "opposite direction", i.e. Ext - DefV,
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// not DefV - Ext, as the getOffsetRange would calculate.
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OffsetRange Uses = getOffsetRange(MI.getOperand(0));
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if (!Uses.contains(Diff))
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dbgs() << "Diff: " << Diff << " out of range " << Uses
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if (!Uses.contains(-Diff))
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dbgs() << "Diff: " << -Diff << " out of range " << Uses
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<< " for " << MI;
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assert(Uses.contains(Diff));
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assert(Uses.contains(-Diff));
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#endif
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MBB.erase(MI);
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return true;
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54
test/CodeGen/Hexagon/cext-opt-range-assert.mir
Normal file
54
test/CodeGen/Hexagon/cext-opt-range-assert.mir
Normal file
@ -0,0 +1,54 @@
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# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s
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# REQUIRES: asserts
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#
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# This testcase used to trigger an incorrect assertion. Make sure it no
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# longer does.
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# CHECK: A2_tfrsi @G + 65536
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--- |
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define void @fred() {
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ret void
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}
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@G = external global [128 x i16], align 8
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...
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---
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name: fred
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1
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%6:intregs = A2_tfrsi @G
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%7:intregs = A2_addi killed %6, 2
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%8:intregs = A2_tfrsi 127
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ADJCALLSTACKDOWN 0, 0, implicit-def %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
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%r0 = COPY %7
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%r1 = COPY %8
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%9:intregs = IMPLICIT_DEF
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J2_callr killed %9, implicit-def dead %pc, implicit-def dead %r31, implicit %r29, implicit %r0, implicit %r1, implicit-def %r29
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ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
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%5:intregs = A2_tfrsi 8
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%10:intregs = A2_tfrsi @G + 8
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%4:intregs = A2_addi killed %10, 2
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bb.1:
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successors: %bb.1, %bb.2
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%0:intregs = PHI %4, %bb.0, %3, %bb.1
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%1:intregs = PHI %5, %bb.0, %2, %bb.1
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%11:predregs = C2_cmpgtui %1, 127
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%2:intregs = A2_addi %1, 8
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%3:intregs = A2_addi %0, 16
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J2_jumpf %11, %bb.1, implicit-def %pc
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bb.2:
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%13:intregs = A2_tfrsi @G
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%14:intregs = A2_addi killed %13, 2
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%15:intregs = A2_tfrsi 127
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ADJCALLSTACKDOWN 0, 0, implicit-def %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
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%r0 = COPY %14
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%r1 = COPY %15
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%16:intregs = IMPLICIT_DEF
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PS_callr_nr killed %16, implicit %r0, implicit %r1, implicit-def %r29
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ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
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...
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