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[TTI][X86] Reordered getCmpSelInstrCost cost tables in descending ISA order. NFCI.
Minor tidyup to make it clearer whats going on before adding additional costs. llvm-svn: 351683
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@ -1650,17 +1650,23 @@ int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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static const CostTblEntry SSE2CostTbl[] = {
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{ ISD::SETCC, MVT::v2i64, 8 },
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{ ISD::SETCC, MVT::v4i32, 1 },
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{ ISD::SETCC, MVT::v8i16, 1 },
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{ ISD::SETCC, MVT::v16i8, 1 },
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static const CostTblEntry AVX512BWCostTbl[] = {
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{ ISD::SETCC, MVT::v32i16, 1 },
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{ ISD::SETCC, MVT::v64i8, 1 },
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};
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static const CostTblEntry SSE42CostTbl[] = {
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{ ISD::SETCC, MVT::v2f64, 1 },
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{ ISD::SETCC, MVT::v4f32, 1 },
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{ ISD::SETCC, MVT::v2i64, 1 },
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static const CostTblEntry AVX512CostTbl[] = {
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{ ISD::SETCC, MVT::v8i64, 1 },
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{ ISD::SETCC, MVT::v16i32, 1 },
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{ ISD::SETCC, MVT::v8f64, 1 },
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{ ISD::SETCC, MVT::v16f32, 1 },
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};
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static const CostTblEntry AVX2CostTbl[] = {
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{ ISD::SETCC, MVT::v4i64, 1 },
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{ ISD::SETCC, MVT::v8i32, 1 },
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{ ISD::SETCC, MVT::v16i16, 1 },
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{ ISD::SETCC, MVT::v32i8, 1 },
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};
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static const CostTblEntry AVX1CostTbl[] = {
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@ -1673,23 +1679,17 @@ int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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{ ISD::SETCC, MVT::v32i8, 4 },
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};
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static const CostTblEntry AVX2CostTbl[] = {
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{ ISD::SETCC, MVT::v4i64, 1 },
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{ ISD::SETCC, MVT::v8i32, 1 },
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{ ISD::SETCC, MVT::v16i16, 1 },
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{ ISD::SETCC, MVT::v32i8, 1 },
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static const CostTblEntry SSE42CostTbl[] = {
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{ ISD::SETCC, MVT::v2f64, 1 },
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{ ISD::SETCC, MVT::v4f32, 1 },
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{ ISD::SETCC, MVT::v2i64, 1 },
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};
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static const CostTblEntry AVX512CostTbl[] = {
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{ ISD::SETCC, MVT::v8i64, 1 },
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{ ISD::SETCC, MVT::v16i32, 1 },
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{ ISD::SETCC, MVT::v8f64, 1 },
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{ ISD::SETCC, MVT::v16f32, 1 },
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};
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static const CostTblEntry AVX512BWCostTbl[] = {
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{ ISD::SETCC, MVT::v32i16, 1 },
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{ ISD::SETCC, MVT::v64i8, 1 },
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static const CostTblEntry SSE2CostTbl[] = {
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{ ISD::SETCC, MVT::v2i64, 8 },
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{ ISD::SETCC, MVT::v4i32, 1 },
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{ ISD::SETCC, MVT::v8i16, 1 },
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{ ISD::SETCC, MVT::v16i8, 1 },
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};
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if (ST->hasBWI())
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