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[CodeGen] Properly propagating Calling Convention information when lowering vector arguments

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When joining the legal parts of vector arguments into its original value
during the lower of Formal Arguments in SelectionDAGBuilder, the Calling
Convention information was not being propagated for the handling of each
individual parts. The same did not happen when lowering calls, causing a
mismatch.

This patch fixes the issue by properly propagating the Calling
Convention details.

This fixes Bugzilla #47001.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D86715
This commit is contained in:
Lucas Prates 2020-08-27 15:31:40 +01:00
parent bce40acc54
commit 4265553ed8
3 changed files with 83 additions and 13 deletions
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4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -389,7 +389,7 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
// as appropriate. // as appropriate.
for (unsigned i = 0; i != NumParts; ++i) for (unsigned i = 0; i != NumParts; ++i)
Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
PartVT, IntermediateVT, V); PartVT, IntermediateVT, V, CallConv);
} else if (NumParts > 0) { } else if (NumParts > 0) {
// If the intermediate type was expanded, build the intermediate // If the intermediate type was expanded, build the intermediate
// operands from the parts. // operands from the parts.
@ -398,7 +398,7 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
unsigned Factor = NumParts / NumIntermediates; unsigned Factor = NumParts / NumIntermediates;
for (unsigned i = 0; i != NumIntermediates; ++i) for (unsigned i = 0; i != NumIntermediates; ++i)
Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
PartVT, IntermediateVT, V); PartVT, IntermediateVT, V, CallConv);
} }
// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the

89
test/CodeGen/ARM/fp16-args.ll
View File

@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT ; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD ; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT ; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-LE
; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD ; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-LE
; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-BE
; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-BE
define half @foo(half %a, half %b) { define half @foo(half %a, half %b) {
; SOFT-LABEL: foo: ; SOFT-LABEL: foo:
@ -44,3 +44,76 @@ entry:
%0 = fadd half %a, %b %0 = fadd half %a, %b
ret half %0 ret half %0
} }
define <4 x half> @foo_vec(<4 x half> %a) {
; SOFT-LABEL: foo_vec:
; SOFT: @ %bb.0: @ %entry
; SOFT-NEXT: vmov s0, r3
; SOFT-NEXT: vmov s2, r1
; SOFT-NEXT: vcvtb.f32.f16 s0, s0
; SOFT-NEXT: vmov s4, r0
; SOFT-NEXT: vcvtb.f32.f16 s2, s2
; SOFT-NEXT: vmov s6, r2
; SOFT-NEXT: vcvtb.f32.f16 s4, s4
; SOFT-NEXT: vcvtb.f32.f16 s6, s6
; SOFT-NEXT: vadd.f32 s0, s0, s0
; SOFT-NEXT: vadd.f32 s2, s2, s2
; SOFT-NEXT: vcvtb.f16.f32 s0, s0
; SOFT-NEXT: vadd.f32 s4, s4, s4
; SOFT-NEXT: vcvtb.f16.f32 s2, s2
; SOFT-NEXT: vadd.f32 s6, s6, s6
; SOFT-NEXT: vcvtb.f16.f32 s4, s4
; SOFT-NEXT: vcvtb.f16.f32 s6, s6
; SOFT-NEXT: vmov r0, s4
; SOFT-NEXT: vmov r1, s2
; SOFT-NEXT: vmov r2, s6
; SOFT-NEXT: vmov r3, s0
; SOFT-NEXT: bx lr
;
; HARD-LABEL: foo_vec:
; HARD: @ %bb.0: @ %entry
; HARD-NEXT: vcvtb.f32.f16 s4, s3
; HARD-NEXT: vcvtb.f32.f16 s2, s2
; HARD-NEXT: vcvtb.f32.f16 s6, s1
; HARD-NEXT: vcvtb.f32.f16 s0, s0
; HARD-NEXT: vadd.f32 s2, s2, s2
; HARD-NEXT: vadd.f32 s0, s0, s0
; HARD-NEXT: vcvtb.f16.f32 s2, s2
; HARD-NEXT: vadd.f32 s4, s4, s4
; HARD-NEXT: vcvtb.f16.f32 s0, s0
; HARD-NEXT: vadd.f32 s6, s6, s6
; HARD-NEXT: vcvtb.f16.f32 s3, s4
; HARD-NEXT: vcvtb.f16.f32 s1, s6
; HARD-NEXT: bx lr
;
; FULL-SOFT-LE-LABEL: foo_vec:
; FULL-SOFT-LE: @ %bb.0: @ %entry
; FULL-SOFT-LE-NEXT: vmov d16, r0, r1
; FULL-SOFT-LE-NEXT: vadd.f16 d16, d16, d16
; FULL-SOFT-LE-NEXT: vmov r0, r1, d16
; FULL-SOFT-LE-NEXT: bx lr
;
; FULL-HARD-LE-LABEL: foo_vec:
; FULL-HARD-LE: @ %bb.0: @ %entry
; FULL-HARD-LE-NEXT: vadd.f16 d0, d0, d0
; FULL-HARD-LE-NEXT: bx lr
;
; FULL-SOFT-BE-LABEL: foo_vec:
; FULL-SOFT-BE: @ %bb.0: @ %entry
; FULL-SOFT-BE-NEXT: vmov d16, r1, r0
; FULL-SOFT-BE-NEXT: vrev64.16 d16, d16
; FULL-SOFT-BE-NEXT: vadd.f16 d16, d16, d16
; FULL-SOFT-BE-NEXT: vrev64.16 d16, d16
; FULL-SOFT-BE-NEXT: vmov r1, r0, d16
; FULL-SOFT-BE-NEXT: bx lr
;
; FULL-HARD-BE-LABEL: foo_vec:
; FULL-HARD-BE: @ %bb.0: @ %entry
; FULL-HARD-BE-NEXT: vrev64.16 d16, d0
; FULL-HARD-BE-NEXT: vadd.f16 d16, d16, d16
; FULL-HARD-BE-NEXT: vrev64.16 d0, d16
; FULL-HARD-BE-NEXT: bx lr
entry:
%0 = fadd <4 x half> %a, %a
ret <4 x half> %0
}

3
test/CodeGen/ARM/fp16-v3.ll
View File

@ -28,9 +28,6 @@ define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
} }
; CHECK-LABEL: test_bitcast: ; CHECK-LABEL: test_bitcast:
; CHECK: vcvtb.f16.f32
; CHECK: vcvtb.f16.f32
; CHECK: vcvtb.f16.f32
; CHECK: pkhbt ; CHECK: pkhbt
; CHECK: uxth ; CHECK: uxth
define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 { define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {