RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

[X86] Fix a few typos in comments.

Browse Source 
llvm-svn: 342829
This commit is contained in:
Craig Topper 2018-09-23 06:49:47 +00:00
parent 7815dbf10d
commit 42725f99d0
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -17308,7 +17308,7 @@ static SDValue LowerZERO_EXTEND_Mask(SDValue Op,
SDLoc DL(Op);
unsigned NumElts = VT.getVectorNumElements();
// For all vectors, but vXi8 we can just emit a sign_extend a shift. This
// For all vectors, but vXi8 we can just emit a sign_extend and a shift. This
// avoids a constant pool load.
if (VT.getVectorElementType() != MVT::i8) {
SDValue Extend = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, In);
@ -19520,7 +19520,7 @@ static SDValue LowerSIGN_EXTEND_Mask(SDValue Op,
unsigned NumElts = VT.getVectorNumElements();
// Extend VT if the scalar type is v8/v16 and BWI is not supported.
// Extend VT if the scalar type is i8/i16 and BWI is not supported.
MVT ExtVT = VT;
if (!Subtarget.hasBWI() && VTElt.getSizeInBits() <= 16) {
// If v16i32 is to be avoided, we'll need to split and concatenate.