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[X86][LegalizeTypes] Add SoftPromoteHalf support STRICT_FP_EXTEND and STRICT_FP_ROUND
This adds a strict version of FP16_TO_FP and FP_TO_FP16 and uses them to implement soft promotion for the half type. This is enough to provide basic support for __fp16 with strictfp. Add the necessary X86 support to use VCVTPS2PH/VCVTPH2PS when F16C is enabled.
This commit is contained in:
Craig Topper
parent
2a138c13f8
commit
42881b3a20
@ -633,6 +633,7 @@ namespace ISD {
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/// form a semi-softened interface for dealing with f16 (as an i16), which
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/// is often a storage-only type but has native conversions.
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FP16_TO_FP, FP_TO_FP16,
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STRICT_FP16_TO_FP, STRICT_FP_TO_FP16,
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/// Perform various unary floating-point operations inspired by libm. For
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/// FPOWI, the result is undefined if if the integer operand doesn't fit
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@ -701,6 +701,8 @@ public:
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switch (NodeType) {
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default:
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return false;
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case ISD::STRICT_FP16_TO_FP:
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case ISD::STRICT_FP_TO_FP16:
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#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
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case ISD::STRICT_##DAGN:
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#include "llvm/IR/ConstrainedOps.def"
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@ -1009,6 +1009,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
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Action = TLI.getOperationAction(Node->getOpcode(),
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Node->getOperand(0).getValueType());
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break;
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case ISD::STRICT_FP_TO_FP16:
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case ISD::STRICT_SINT_TO_FP:
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case ISD::STRICT_UINT_TO_FP:
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case ISD::STRICT_LRINT:
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@ -3272,6 +3273,21 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
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}
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break;
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case ISD::STRICT_FP16_TO_FP:
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if (Node->getValueType(0) != MVT::f32) {
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// We can extend to types bigger than f32 in two steps without changing
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// the result. Since "f16 -> f32" is much more commonly available, give
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// CodeGen the option of emitting that before resorting to a libcall.
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SDValue Res =
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DAG.getNode(ISD::STRICT_FP16_TO_FP, dl, {MVT::f32, MVT::Other},
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{Node->getOperand(0), Node->getOperand(1)});
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Res = DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
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{Node->getValueType(0), MVT::Other},
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{Res.getValue(1), Res});
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Results.push_back(Res);
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Results.push_back(Res.getValue(1));
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}
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break;
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case ISD::FP_TO_FP16:
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LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
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if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
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@ -4234,6 +4250,17 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
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Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
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}
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break;
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case ISD::STRICT_FP16_TO_FP: {
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if (Node->getValueType(0) == MVT::f32) {
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TargetLowering::MakeLibCallOptions CallOptions;
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std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
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DAG, RTLIB::FPEXT_F16_F32, MVT::f32, Node->getOperand(1), CallOptions,
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SDLoc(Node), Node->getOperand(0));
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Results.push_back(Tmp.first);
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Results.push_back(Tmp.second);
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}
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break;
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}
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case ISD::FP_TO_FP16: {
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RTLIB::Libcall LC =
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RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
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@ -4241,6 +4268,19 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
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Results.push_back(ExpandLibCall(LC, Node, false));
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break;
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}
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case ISD::STRICT_FP_TO_FP16: {
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RTLIB::Libcall LC =
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RTLIB::getFPROUND(Node->getOperand(1).getValueType(), MVT::f16);
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assert(LC != RTLIB::UNKNOWN_LIBCALL &&
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"Unable to expand strict_fp_to_fp16");
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TargetLowering::MakeLibCallOptions CallOptions;
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std::pair<SDValue, SDValue> Tmp =
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TLI.makeLibCall(DAG, LC, Node->getValueType(0), Node->getOperand(1),
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CallOptions, SDLoc(Node), Node->getOperand(0));
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Results.push_back(Tmp.first);
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Results.push_back(Tmp.second);
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break;
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}
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case ISD::FSUB:
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case ISD::STRICT_FSUB:
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ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
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@ -2440,6 +2440,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
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case ISD::EXTRACT_VECTOR_ELT:
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R = SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(N); break;
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case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break;
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case ISD::STRICT_FP_ROUND:
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case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break;
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// Unary FP Operations
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@ -2592,6 +2593,14 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FPOWI(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FP_ROUND(SDNode *N) {
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if (N->isStrictFPOpcode()) {
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SDValue Res =
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DAG.getNode(ISD::STRICT_FP_TO_FP16, SDLoc(N), {MVT::i16, MVT::Other},
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{N->getOperand(0), N->getOperand(1)});
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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return Res;
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}
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return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), MVT::i16, N->getOperand(0));
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}
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@ -2701,6 +2710,7 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
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case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
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case ISD::STRICT_FP_EXTEND:
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case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break;
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case ISD::SELECT_CC: Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break;
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case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break;
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@ -2741,7 +2751,18 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FCOPYSIGN(SDNode *N,
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}
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SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
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SDValue Op = GetSoftPromotedHalf(N->getOperand(0));
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bool IsStrict = N->isStrictFPOpcode();
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SDValue Op = GetSoftPromotedHalf(N->getOperand(IsStrict ? 1 : 0));
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if (IsStrict) {
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SDValue Res =
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DAG.getNode(ISD::STRICT_FP16_TO_FP, SDLoc(N),
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{N->getValueType(0), MVT::Other}, {N->getOperand(0), Op});
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ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
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ReplaceValueWith(SDValue(N, 0), Res);
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return SDValue();
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}
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return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), Op);
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}
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@ -342,7 +342,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::BITCAST: return "bitcast";
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case ISD::ADDRSPACECAST: return "addrspacecast";
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case ISD::FP16_TO_FP: return "fp16_to_fp";
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case ISD::STRICT_FP16_TO_FP: return "strict_fp16_to_fp";
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case ISD::FP_TO_FP16: return "fp_to_fp16";
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case ISD::STRICT_FP_TO_FP16: return "strict_fp_to_fp16";
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case ISD::LROUND: return "lround";
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case ISD::STRICT_LROUND: return "strict_lround";
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case ISD::LLROUND: return "llround";
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@ -374,20 +374,30 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// If we don't have F16C support, then lower half float conversions
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// into library calls.
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if (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) {
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom);
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setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f32, Custom);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f32, Custom);
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} else {
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
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setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
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setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f32, Expand);
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}
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// There's never any support for operations beyond MVT::f32.
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setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
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setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
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setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
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setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f64, Expand);
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setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f80, Expand);
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setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f128, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
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setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f64, Expand);
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setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f80, Expand);
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setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f128, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
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@ -20553,29 +20563,64 @@ SDValue X86TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
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}
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static SDValue LowerFP16_TO_FP(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getOperand(0).getValueType() == MVT::i16 &&
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Op.getValueType() == MVT::f32 && "Unexpected VT!");
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bool IsStrict = Op->isStrictFPOpcode();
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SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
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assert(Src.getValueType() == MVT::i16 && Op.getValueType() == MVT::f32 &&
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"Unexpected VT!");
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SDLoc dl(Op);
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SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16,
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DAG.getConstant(0, dl, MVT::v8i16),
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Op.getOperand(0), DAG.getIntPtrConstant(0, dl));
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Res = DAG.getNode(X86ISD::CVTPH2PS, dl, MVT::v4f32, Res);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
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DAG.getIntPtrConstant(0, dl));
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DAG.getConstant(0, dl, MVT::v8i16), Src,
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DAG.getIntPtrConstant(0, dl));
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SDValue Chain;
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if (IsStrict) {
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Res = DAG.getNode(X86ISD::STRICT_CVTPH2PS, dl, {MVT::v4f32, MVT::Other},
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{Op.getOperand(0), Res});
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Chain = Res.getValue(1);
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} else {
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Res = DAG.getNode(X86ISD::CVTPH2PS, dl, MVT::v4f32, Res);
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}
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Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
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DAG.getIntPtrConstant(0, dl));
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if (IsStrict)
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return DAG.getMergeValues({Res, Chain}, dl);
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return Res;
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}
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static SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) {
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assert(Op.getOperand(0).getValueType() == MVT::f32 &&
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Op.getValueType() == MVT::i16 && "Unexpected VT!");
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bool IsStrict = Op->isStrictFPOpcode();
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SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
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assert(Src.getValueType() == MVT::f32 && Op.getValueType() == MVT::i16 &&
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"Unexpected VT!");
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SDLoc dl(Op);
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SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32,
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Op.getOperand(0));
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Res = DAG.getNode(X86ISD::CVTPS2PH, dl, MVT::v8i16, Res,
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DAG.getTargetConstant(4, dl, MVT::i32));
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Res,
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DAG.getIntPtrConstant(0, dl));
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SDValue Res, Chain;
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if (IsStrict) {
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Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4f32,
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DAG.getConstantFP(0, dl, MVT::v4f32), Src,
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DAG.getIntPtrConstant(0, dl));
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Res = DAG.getNode(
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X86ISD::STRICT_CVTPS2PH, dl, {MVT::v8i16, MVT::Other},
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{Op.getOperand(0), Res, DAG.getTargetConstant(4, dl, MVT::i32)});
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Chain = Res.getValue(1);
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} else {
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// FIXME: Should we use zeros for upper elements for non-strict?
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Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, Src);
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Res = DAG.getNode(X86ISD::CVTPS2PH, dl, MVT::v8i16, Res,
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DAG.getTargetConstant(4, dl, MVT::i32));
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}
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Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Res,
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DAG.getIntPtrConstant(0, dl));
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if (IsStrict)
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return DAG.getMergeValues({Res, Chain}, dl);
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return Res;
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}
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/// Depending on uarch and/or optimizing for size, we might prefer to use a
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@ -28821,8 +28866,10 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::STRICT_FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
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case ISD::FP_ROUND:
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case ISD::STRICT_FP_ROUND: return LowerFP_ROUND(Op, DAG);
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case ISD::FP16_TO_FP: return LowerFP16_TO_FP(Op, DAG);
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case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
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case ISD::FP16_TO_FP:
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case ISD::STRICT_FP16_TO_FP: return LowerFP16_TO_FP(Op, DAG);
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case ISD::FP_TO_FP16:
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case ISD::STRICT_FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG);
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case ISD::LOAD: return LowerLoad(Op, Subtarget, DAG);
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case ISD::STORE: return LowerStore(Op, Subtarget, DAG);
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case ISD::FADD:
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@ -30162,8 +30209,10 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(SCALAR_UINT_TO_FP)
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NODE_NAME_CASE(SCALAR_UINT_TO_FP_RND)
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NODE_NAME_CASE(CVTPS2PH)
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NODE_NAME_CASE(STRICT_CVTPS2PH)
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NODE_NAME_CASE(MCVTPS2PH)
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NODE_NAME_CASE(CVTPH2PS)
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NODE_NAME_CASE(STRICT_CVTPH2PS)
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NODE_NAME_CASE(CVTPH2PS_SAE)
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NODE_NAME_CASE(CVTP2SI)
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NODE_NAME_CASE(CVTP2UI)
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@ -627,6 +627,9 @@ namespace llvm {
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// Strict FMA nodes.
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STRICT_FNMADD, STRICT_FMSUB, STRICT_FNMSUB,
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// Conversions between float and half-float.
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STRICT_CVTPS2PH, STRICT_CVTPH2PS,
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// Compare and swap.
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LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LCMPXCHG8_DAG,
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@ -8568,14 +8568,15 @@ let Uses = [MXCSR], mayRaiseFPException = 1 in
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multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
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X86MemOperand x86memop, PatFrag ld_frag,
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X86FoldableSchedWrite sched> {
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defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst),
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defm rr : AVX512_maskable_split<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst),
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(ins _src.RC:$src), "vcvtph2ps", "$src", "$src",
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(X86any_cvtph2ps (_src.VT _src.RC:$src)),
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(X86cvtph2ps (_src.VT _src.RC:$src))>,
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T8PD, Sched<[sched]>;
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defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst),
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defm rm : AVX512_maskable_split<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst),
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(ins x86memop:$src), "vcvtph2ps", "$src", "$src",
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(X86cvtph2ps (_src.VT
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(ld_frag addr:$src)))>,
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(X86any_cvtph2ps (_src.VT (ld_frag addr:$src))),
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(X86cvtph2ps (_src.VT (ld_frag addr:$src)))>,
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T8PD, Sched<[sched.Folded]>;
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}
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@ -8604,9 +8605,9 @@ let Predicates = [HasVLX] in {
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EVEX_CD8<32, CD8VH>;
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// Pattern match vcvtph2ps of a scalar i64 load.
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def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))),
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def : Pat<(v4f32 (X86any_cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))),
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(VCVTPH2PSZ128rm addr:$src)>;
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def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert
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def : Pat<(v4f32 (X86any_cvtph2ps (v8i16 (bitconvert
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(v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(VCVTPH2PSZ128rm addr:$src)>;
|
||||
}
|
||||
@ -8618,7 +8619,7 @@ let ExeDomain = GenericDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
|
||||
(ins _src.RC:$src1, i32u8imm:$src2),
|
||||
"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set _dest.RC:$dst,
|
||||
(X86cvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2)))]>,
|
||||
(X86any_cvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2)))]>,
|
||||
Sched<[RR]>;
|
||||
let Constraints = "$src0 = $dst" in
|
||||
def rrk : AVX512AIi8<0x1D, MRMDestReg, (outs _dest.RC:$dst),
|
||||
@ -8673,16 +8674,16 @@ let Predicates = [HasAVX512] in {
|
||||
}
|
||||
|
||||
def : Pat<(store (f64 (extractelt
|
||||
(bc_v2f64 (v8i16 (X86cvtps2ph VR128X:$src1, timm:$src2))),
|
||||
(bc_v2f64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))),
|
||||
(iPTR 0))), addr:$dst),
|
||||
(VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>;
|
||||
def : Pat<(store (i64 (extractelt
|
||||
(bc_v2i64 (v8i16 (X86cvtps2ph VR128X:$src1, timm:$src2))),
|
||||
(bc_v2i64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))),
|
||||
(iPTR 0))), addr:$dst),
|
||||
(VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>;
|
||||
def : Pat<(store (v8i16 (X86cvtps2ph VR256X:$src1, timm:$src2)), addr:$dst),
|
||||
def : Pat<(store (v8i16 (X86any_cvtps2ph VR256X:$src1, timm:$src2)), addr:$dst),
|
||||
(VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, timm:$src2)>;
|
||||
def : Pat<(store (v16i16 (X86cvtps2ph VR512:$src1, timm:$src2)), addr:$dst),
|
||||
def : Pat<(store (v16i16 (X86any_cvtps2ph VR512:$src1, timm:$src2)), addr:$dst),
|
||||
(VCVTPS2PHZmr addr:$dst, VR512:$src1, timm:$src2)>;
|
||||
}
|
||||
|
||||
|
||||
@ -721,19 +721,27 @@ def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>;
|
||||
def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
|
||||
def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>;
|
||||
|
||||
def SDTcvtph2ps : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
|
||||
SDTCVecEltisVT<1, i16>]>;
|
||||
def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", SDTcvtph2ps>;
|
||||
def X86strict_cvtph2ps : SDNode<"X86ISD::STRICT_CVTPH2PS", SDTcvtph2ps,
|
||||
[SDNPHasChain]>;
|
||||
def X86any_cvtph2ps : PatFrags<(ops node:$src),
|
||||
[(X86strict_cvtph2ps node:$src),
|
||||
(X86cvtph2ps node:$src)]>;
|
||||
|
||||
def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS",
|
||||
SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
|
||||
SDTCVecEltisVT<1, i16>]> >;
|
||||
def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", SDTcvtph2ps>;
|
||||
|
||||
def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE",
|
||||
SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
|
||||
SDTCVecEltisVT<1, i16>]> >;
|
||||
def SDTcvtps2ph : SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
|
||||
SDTCVecEltisVT<1, f32>,
|
||||
SDTCisVT<2, i32>]>;
|
||||
def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", SDTcvtps2ph>;
|
||||
def X86strict_cvtps2ph : SDNode<"X86ISD::STRICT_CVTPS2PH", SDTcvtps2ph,
|
||||
[SDNPHasChain]>;
|
||||
def X86any_cvtps2ph : PatFrags<(ops node:$src1, node:$src2),
|
||||
[(X86strict_cvtps2ph node:$src1, node:$src2),
|
||||
(X86cvtps2ph node:$src1, node:$src2)]>;
|
||||
|
||||
def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH",
|
||||
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
|
||||
SDTCVecEltisVT<1, f32>,
|
||||
SDTCisVT<2, i32>]> >;
|
||||
def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH",
|
||||
SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>,
|
||||
SDTCVecEltisVT<1, f32>,
|
||||
|
||||
@ -7337,12 +7337,12 @@ multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop,
|
||||
X86FoldableSchedWrite sched> {
|
||||
def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
|
||||
"vcvtph2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set RC:$dst, (X86cvtph2ps VR128:$src))]>,
|
||||
[(set RC:$dst, (X86any_cvtph2ps VR128:$src))]>,
|
||||
T8PD, VEX, Sched<[sched]>;
|
||||
let hasSideEffects = 0, mayLoad = 1 in
|
||||
def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
|
||||
"vcvtph2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set RC:$dst, (X86cvtph2ps (loadv8i16 addr:$src)))]>,
|
||||
[(set RC:$dst, (X86any_cvtph2ps (loadv8i16 addr:$src)))]>,
|
||||
T8PD, VEX, Sched<[sched.Folded]>;
|
||||
}
|
||||
|
||||
@ -7351,7 +7351,7 @@ multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop,
|
||||
def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
|
||||
(ins RC:$src1, i32u8imm:$src2),
|
||||
"vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (X86cvtps2ph RC:$src1, timm:$src2))]>,
|
||||
[(set VR128:$dst, (X86any_cvtps2ph RC:$src1, timm:$src2))]>,
|
||||
TAPD, VEX, Sched<[RR]>;
|
||||
let hasSideEffects = 0, mayStore = 1 in
|
||||
def mr : Ii8<0x1D, MRMDestMem, (outs),
|
||||
@ -7369,21 +7369,21 @@ let Predicates = [HasF16C, NoVLX] in {
|
||||
WriteCvtPS2PHYSt>, VEX_L, SIMD_EXC;
|
||||
|
||||
// Pattern match vcvtph2ps of a scalar i64 load.
|
||||
def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))),
|
||||
def : Pat<(v4f32 (X86any_cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))),
|
||||
(VCVTPH2PSrm addr:$src)>;
|
||||
def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16
|
||||
def : Pat<(v4f32 (X86any_cvtph2ps (bc_v8i16
|
||||
(v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
|
||||
(VCVTPH2PSrm addr:$src)>;
|
||||
|
||||
def : Pat<(store (f64 (extractelt
|
||||
(bc_v2f64 (v8i16 (X86cvtps2ph VR128:$src1, timm:$src2))),
|
||||
(bc_v2f64 (v8i16 (X86any_cvtps2ph VR128:$src1, timm:$src2))),
|
||||
(iPTR 0))), addr:$dst),
|
||||
(VCVTPS2PHmr addr:$dst, VR128:$src1, timm:$src2)>;
|
||||
def : Pat<(store (i64 (extractelt
|
||||
(bc_v2i64 (v8i16 (X86cvtps2ph VR128:$src1, timm:$src2))),
|
||||
(bc_v2i64 (v8i16 (X86any_cvtps2ph VR128:$src1, timm:$src2))),
|
||||
(iPTR 0))), addr:$dst),
|
||||
(VCVTPS2PHmr addr:$dst, VR128:$src1, timm:$src2)>;
|
||||
def : Pat<(store (v8i16 (X86cvtps2ph VR256:$src1, timm:$src2)), addr:$dst),
|
||||
def : Pat<(store (v8i16 (X86any_cvtps2ph VR256:$src1, timm:$src2)), addr:$dst),
|
||||
(VCVTPS2PHYmr addr:$dst, VR256:$src1, timm:$src2)>;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user