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[X86] Make inline assembly 'x' and 'v' constraints work for f128.
Including a type legalizer fix to make bitcast operand promotion work correctly when getSoftenedFloat returns f128 instead of i128. Fixes PR43157 llvm-svn: 370293
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@ -895,8 +895,12 @@ bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo) {
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}
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SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
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return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
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GetSoftenedFloat(N->getOperand(0)));
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SDValue Op0 = GetSoftenedFloat(N->getOperand(0));
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if (Op0 == N->getOperand(0))
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return SDValue();
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return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0);
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}
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SDValue DAGTypeLegalizer::SoftenFloatOp_COPY_TO_REG(SDNode *N) {
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@ -45784,8 +45784,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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if (VConstraint && Subtarget.hasVLX())
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return std::make_pair(0U, &X86::FR64XRegClass);
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return std::make_pair(0U, &X86::FR64RegClass);
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// TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
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// Vector types.
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// TODO: Handle i128 in FR128RegClass after it is tested well.
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// Vector types and fp128.
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case MVT::f128:
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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20
test/CodeGen/X86/pr43157.ll
Normal file
20
test/CodeGen/X86/pr43157.ll
Normal file
@ -0,0 +1,20 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-pc-linux -o - -mattr=+mmx | FileCheck %s
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define void @foo(fp128 %x) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: movaps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: callq __multf3
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: popq %rax
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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entry:
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%mul = fmul fp128 %x, 0xL00000000000000003FFF800000000000
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tail call void asm sideeffect "", "x,~{dirflag},~{fpsr},~{flags}"(fp128 %mul)
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ret void
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}
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