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[X86] Make inline assembly 'x' and 'v' constraints work for f128.

Including a type legalizer fix to make bitcast operand promotion
work correctly when getSoftenedFloat returns f128 instead of i128.

Fixes PR43157

llvm-svn: 370293
This commit is contained in:
Craig Topper 2019-08-29 05:13:56 +00:00
parent 3122150e98
commit 429061bb78
3 changed files with 29 additions and 4 deletions

View File

@ -895,8 +895,12 @@ bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo) {
}
SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
GetSoftenedFloat(N->getOperand(0)));
SDValue Op0 = GetSoftenedFloat(N->getOperand(0));
if (Op0 == N->getOperand(0))
return SDValue();
return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0);
}
SDValue DAGTypeLegalizer::SoftenFloatOp_COPY_TO_REG(SDNode *N) {

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@ -45784,8 +45784,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (VConstraint && Subtarget.hasVLX())
return std::make_pair(0U, &X86::FR64XRegClass);
return std::make_pair(0U, &X86::FR64RegClass);
// TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
// Vector types.
// TODO: Handle i128 in FR128RegClass after it is tested well.
// Vector types and fp128.
case MVT::f128:
case MVT::v16i8:
case MVT::v8i16:
case MVT::v4i32:

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@ -0,0 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-pc-linux -o - -mattr=+mmx | FileCheck %s
define void @foo(fp128 %x) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movaps {{.*}}(%rip), %xmm1
; CHECK-NEXT: callq __multf3
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%mul = fmul fp128 %x, 0xL00000000000000003FFF800000000000
tail call void asm sideeffect "", "x,~{dirflag},~{fpsr},~{flags}"(fp128 %mul)
ret void
}