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[VE] Add vector merger operation instructions
Add VMRG/VSHF/VCP/VEX isntructions. Add regression tests too. Also add new patterns to parse new UImm4 oeprand. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D90292
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@ -280,6 +280,17 @@ public:
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}
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return false;
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}
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bool isUImm4() {
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if (!isImm())
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return false;
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// Constant case
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if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
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int64_t Value = ConstExpr->getValue();
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return isUInt<4>(Value);
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}
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return false;
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}
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bool isUImm6() {
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if (!isImm())
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return false;
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@ -479,6 +490,10 @@ public:
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addImmOperands(Inst, N);
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}
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void addUImm4Operands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addUImm6Operands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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@ -157,6 +157,15 @@ def uimm3 : Operand<i32>, PatLeaf<(imm), [{
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let ParserMatchClass = UImm3AsmOperand;
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}
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// uimm4 - Generic immediate value.
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def UImm4AsmOperand : AsmOperandClass {
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let Name = "UImm4";
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}
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def uimm4 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<4>(N->getZExtValue()); }], ULO7> {
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let ParserMatchClass = UImm4AsmOperand;
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}
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// uimm6 - Generic immediate value.
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def UImm6AsmOperand : AsmOperandClass {
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let Name = "UImm6";
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@ -644,6 +644,16 @@ multiclass RVI3m<string opcStr, bits<8>opc, RegisterClass VRC,
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defm vvi : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC,
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(ins VRC:$vy, VRC:$vz, simm7fp:$sy)>;
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}
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// special RV multiclass with 3 arguments for VSHF.
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// e.g. VSHF
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let vy = ?, vz = ?, VE_VLIndex = 4 in
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multiclass RVSHFm<string opcStr, bits<8>opc, RegisterClass RC,
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Operand SIMM = uimm4> {
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defm vvr : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
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(ins RC:$vy, RC:$vz, I64:$sy)>;
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let cy = 0 in defm vvi : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
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(ins RC:$vy, RC:$vz, SIMM:$sy)>;
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}
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// Section 8.10.1 - VADD (Vector Add)
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let cx = 0, cx2 = 0 in
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@ -1261,3 +1271,22 @@ let cx = 1 in defm VFIMAS : RVI3m<"vfima.s", 0xef, V64, F32>;
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// Section 8.15.7 - VFIMS (Vector Floating Iteration Multiply and Subtract)
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let cx = 0 in defm VFIMSD : RVI3m<"vfims.d", 0xff, V64, I64>;
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let cx = 1 in defm VFIMSS : RVI3m<"vfims.s", 0xff, V64, F32>;
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//-----------------------------------------------------------------------------
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// Section 8.16 - Vector Merger Operation Instructions
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//-----------------------------------------------------------------------------
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// Section 8.16.1 - VMRG (Vector Merge)
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let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>;
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// FIXME: vmrg.w should be called as pvmrg, but following assembly manual.
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let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>;
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def : MnemonicAlias<"vmrg.l", "vmrg">;
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// Section 8.16.2 - VSHF (Vector Shuffle)
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defm VSHF : RVSHFm<"vshf", 0xbc, V64>;
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// Section 8.16.3 - VCP (Vector Compress)
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defm VCP : RV1m<"vcp", 0x8d, V64, VM>;
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// Section 8.16.4 - VEX (Vector Expand)
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defm VEX : RV1m<"vex", 0x9d, V64, VM>;
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28
test/MC/VE/VCP.s
Normal file
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test/MC/VE/VCP.s
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vcp %v11, %v22
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x00,0x8d]
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vcp %v11, %v22
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# CHECK-INST: vcp %vix, %vix
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# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0xff,0x00,0x00,0x00,0x8d]
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vcp %vix, %vix
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# CHECK-INST: vcp %vix, %v22
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x00,0x00,0x8d]
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vcp %vix, %v22
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# CHECK-INST: vcp %v11, %v22, %vm11
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x0b,0x8d]
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vcp %v11, %v22, %vm11
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# CHECK-INST: vcp %v11, %vix, %vm11
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# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0x0b,0x00,0x00,0x0b,0x8d]
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vcp %v11, %vix, %vm11
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# CHECK-INST: vcp %v12, %v20, %vm12
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# CHECK-ENCODING: encoding: [0x00,0x14,0x00,0x0c,0x00,0x00,0x0c,0x8d]
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vcp %v12, %v20, %vm12
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28
test/MC/VE/VEX.s
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28
test/MC/VE/VEX.s
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@ -0,0 +1,28 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vex %v11, %v22
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x00,0x9d]
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vex %v11, %v22
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# CHECK-INST: vex %vix, %vix
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# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0xff,0x00,0x00,0x00,0x9d]
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vex %vix, %vix
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# CHECK-INST: vex %vix, %v22
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x00,0x00,0x9d]
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vex %vix, %v22
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# CHECK-INST: vex %v11, %v22, %vm11
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x00,0x0b,0x9d]
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vex %v11, %v22, %vm11
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# CHECK-INST: vex %v11, %vix, %vm11
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# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0x0b,0x00,0x00,0x0b,0x9d]
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vex %v11, %vix, %vm11
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# CHECK-INST: vex %v12, %v20, %vm12
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# CHECK-ENCODING: encoding: [0x00,0x14,0x00,0x0c,0x00,0x00,0x0c,0x9d]
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vex %v12, %v20, %vm12
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24
test/MC/VE/VMRG.s
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24
test/MC/VE/VMRG.s
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@ -0,0 +1,24 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vmrg %v11, %s20, %v22
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xd6]
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vmrg %v11, %s20, %v22
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# CHECK-INST: vmrg %vix, %vix, %vix
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# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xd6]
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vmrg.l %vix, %vix, %vix
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# CHECK-INST: vmrg.w %vix, -64, %v22
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x40,0xa0,0xd6]
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vmrg.w %vix, -64, %v22
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# CHECK-INST: vmrg %v11, 63, %v22, %vm11
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# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x3f,0x2b,0xd6]
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vmrg.l %v11, 63, %v22, %vm11
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# CHECK-INST: vmrg.w %v11, %v23, %v22, %vm12
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# CHECK-ENCODING: encoding: [0x00,0x16,0x17,0x0b,0x00,0x00,0x8c,0xd6]
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vmrg.w %v11, %v23, %v22, %vm12
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test/MC/VE/VSHF.s
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test/MC/VE/VSHF.s
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@ -0,0 +1,24 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vshf %v11, %v20, %v22, %s20
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# CHECK-ENCODING: encoding: [0x00,0x16,0x14,0x0b,0x00,0x94,0x00,0xbc]
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vshf %v11, %v20, %v22, %s20
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# CHECK-INST: vshf %vix, %vix, %vix, 0
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# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xbc]
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vshf %vix, %vix, %vix, 0
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# CHECK-INST: vshf %vix, %vix, %v22, 15
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# CHECK-ENCODING: encoding: [0x00,0x16,0xff,0xff,0x00,0x0f,0x00,0xbc]
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vshf %vix, %vix, %v22, 15
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# CHECK-INST: vshf %v11, %vix, %v22, 12
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# CHECK-ENCODING: encoding: [0x00,0x16,0xff,0x0b,0x00,0x0c,0x00,0xbc]
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vshf %v11, %vix, %v22, 12
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# CHECK-INST: vshf %v11, %v23, %v22, %s63
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# CHECK-ENCODING: encoding: [0x00,0x16,0x17,0x0b,0x00,0xbf,0x00,0xbc]
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vshf %v11, %v23, %v22, %s63
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