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[PowerPC] Regenerate cmpb tests

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Helps to reduce diff in D90113
This commit is contained in:
Simon Pilgrim 2020-12-02 17:49:00 +00:00
parent 3effbaa68f
commit 42a8d060f0
2 changed files with 53 additions and 53 deletions
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20
test/CodeGen/PowerPC/cmpb-ppc32.ll
View File

@ -1,9 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-p:32:32-i64:64-n32"
target triple = "powerpc-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: blr
entry:
%0 = xor i16 %y, %x
%1 = and i16 %0, 255
@ -14,14 +20,13 @@ entry:
%or = or i32 %conv25, %conv27
%conv29 = trunc i32 %or to i16
ret i16 %conv29
; CHECK-LABEL: @test16
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: clrlwi 3, [[REG1]], 16
; CHECK: blr
}
define i32 @test32(i32 %x, i32 %y) #0 {
; CHECK-LABEL: test32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: blr
entry:
%0 = xor i32 %y, %x
%1 = and i32 %0, 255
@ -39,11 +44,6 @@ entry:
%or49 = or i32 %or, %conv44
%or52 = or i32 %or49, %conv47
ret i32 %or52
; CHECK-LABEL: @test32
; CHECK: cmpb 3, 4, 3
; CHECK-NOT: rlwinm
; CHECK: blr
}
attributes #0 = { nounwind readnone }

86
test/CodeGen/PowerPC/cmpb.ll
View File

@ -1,9 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone
define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 {
; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: clrldi 3, 3, 48
; CHECK-NEXT: blr
entry:
%0 = xor i16 %y, %x
%1 = and i16 %0, 255
@ -14,14 +20,14 @@ entry:
%or = or i32 %conv25, %conv27
%conv29 = trunc i32 %or to i16
ret i16 %conv29
; CHECK-LABEL: @test16
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: clrldi 3, [[REG1]], 48
; CHECK: blr
}
define zeroext i16 @test16p1(i16 zeroext %x, i16 zeroext %y) #0 {
; CHECK-LABEL: test16p1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: andi. 3, 3, 65285
; CHECK-NEXT: blr
entry:
%0 = xor i16 %y, %x
%1 = and i16 %0, 255
@ -32,15 +38,15 @@ entry:
%or = or i32 %conv28, %conv30
%conv32 = trunc i32 %or to i16
ret i16 %conv32
; CHECK-LABEL: @test16p1
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: andi. 3, [[REG1]], 65285
; CHECK: blr
}
; Function Attrs: nounwind readnone
define zeroext i16 @test16p2(i16 zeroext %x, i16 zeroext %y) #0 {
; CHECK-LABEL: test16p2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: andi. 3, 3, 1535
; CHECK-NEXT: blr
entry:
%0 = xor i16 %y, %x
%1 = and i16 %0, 255
@ -51,15 +57,16 @@ entry:
%or = or i32 %conv28, %conv30
%conv32 = trunc i32 %or to i16
ret i16 %conv32
; CHECK-LABEL: @test16p2
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: andi. 3, [[REG1]], 1535
; CHECK: blr
}
; Function Attrs: nounwind readnone
define zeroext i16 @test16p3(i16 zeroext %x, i16 zeroext %y) #0 {
; CHECK-LABEL: test16p3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: clrldi 3, 3, 55
; CHECK-NEXT: xori 3, 3, 1280
; CHECK-NEXT: blr
entry:
%0 = xor i16 %y, %x
%1 = and i16 %0, 255
@ -70,15 +77,14 @@ entry:
%or = or i32 %conv27, %conv29
%conv31 = trunc i32 %or to i16
ret i16 %conv31
; CHECK-LABEL: @test16p3
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: clrldi [[REG2:[0-9]+]], [[REG1]], 55
; CHECK: xori 3, [[REG2]], 1280
; CHECK: blr
}
define zeroext i32 @test32(i32 zeroext %x, i32 zeroext %y) #0 {
; CHECK-LABEL: test32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
entry:
%0 = xor i32 %y, %x
%1 = and i32 %0, 255
@ -96,14 +102,15 @@ entry:
%or49 = or i32 %or, %conv44
%or52 = or i32 %or49, %conv47
ret i32 %or52
; CHECK-LABEL: @test32
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: clrldi 3, [[REG1]], 32
; CHECK: blr
}
define zeroext i32 @test32p1(i32 zeroext %x, i32 zeroext %y) #0 {
; CHECK-LABEL: test32p1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: rldicl 3, 3, 40, 5
; CHECK-NEXT: rldicl 3, 3, 24, 32
; CHECK-NEXT: blr
entry:
%0 = xor i32 %y, %x
%1 = and i32 %0, 255
@ -121,15 +128,15 @@ entry:
%or52 = or i32 %or, %conv47
%or55 = or i32 %or52, %conv50
ret i32 %or55
; CHECK-LABEL: @test32p1
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 40, 5
; CHECK: rldicl 3, [[REG2]], 24, 32
; CHECK: blr
}
define zeroext i32 @test32p2(i32 zeroext %x, i32 zeroext %y) #0 {
; CHECK-LABEL: test32p2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 4, 3
; CHECK-NEXT: rldicl 3, 3, 40, 8
; CHECK-NEXT: rldicl 3, 3, 24, 32
; CHECK-NEXT: blr
entry:
%0 = xor i32 %y, %x
%1 = and i32 %0, 255
@ -143,15 +150,13 @@ entry:
%or = or i32 %conv33, %conv35
%or37 = or i32 %or, %conv32
ret i32 %or37
; CHECK-LABEL: @test32p2
; CHECK: cmpb [[REG1:[0-9]+]], 4, 3
; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 40, 8
; CHECK: rldicl 3, [[REG2]], 24, 32
; CHECK: blr
}
define i64 @test64(i64 %x, i64 %y) #0 {
; CHECK-LABEL: test64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb 3, 3, 4
; CHECK-NEXT: blr
entry:
%shr19 = lshr i64 %x, 56
%conv21 = trunc i64 %shr19 to i32
@ -189,11 +194,6 @@ entry:
%conv110 = select i1 %cmp88, i64 -72057594037927936, i64 0
%or112 = or i64 %or109, %conv110
ret i64 %or112
; CHECK-LABEL: @test64
; CHECK: cmpb 3, 3, 4
; CHECK-NOT: rldicl
; CHECK: blr
}
attributes #0 = { nounwind readnone }