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https://github.com/RPCS3/llvm-mirror.git
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[VectorCombine] Simplify to scalar store if only one element updated
This patch simplifies load-insertelt-store pattern into getelementptr-store. Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D98240
This commit is contained in:
Qiu Chaofan
parent
38ab3a2d9f
commit
42b67ab7d1
@ -50,14 +50,18 @@ static cl::opt<bool> DisableBinopExtractShuffle(
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"disable-binop-extract-shuffle", cl::init(false), cl::Hidden,
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cl::desc("Disable binop extract to shuffle transforms"));
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static cl::opt<unsigned> MaxInstrsToScan(
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"vector-combine-max-scan-instrs", cl::init(30), cl::Hidden,
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cl::desc("Max number of instructions to scan for vector combining."));
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static const unsigned InvalidIndex = std::numeric_limits<unsigned>::max();
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namespace {
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class VectorCombine {
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public:
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VectorCombine(Function &F, const TargetTransformInfo &TTI,
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const DominatorTree &DT)
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: F(F), Builder(F.getContext()), TTI(TTI), DT(DT) {}
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const DominatorTree &DT, AAResults &AA)
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: F(F), Builder(F.getContext()), TTI(TTI), DT(DT), AA(AA) {}
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bool run();
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@ -66,6 +70,7 @@ private:
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IRBuilder<> Builder;
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const TargetTransformInfo &TTI;
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const DominatorTree &DT;
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AAResults &AA;
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bool vectorizeLoadInsert(Instruction &I);
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ExtractElementInst *getShuffleExtract(ExtractElementInst *Ext0,
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@ -83,6 +88,7 @@ private:
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bool foldBitcastShuf(Instruction &I);
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bool scalarizeBinopOrCmp(Instruction &I);
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bool foldExtractedCmps(Instruction &I);
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bool foldSingleElementStore(Instruction &I);
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};
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} // namespace
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@ -754,6 +760,66 @@ bool VectorCombine::foldExtractedCmps(Instruction &I) {
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return true;
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}
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// Check if memory loc modified between two instrs in the same BB
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static bool isMemModifiedBetween(BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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const MemoryLocation &Loc, AAResults &AA) {
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unsigned NumScanned = 0;
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return std::any_of(Begin, End, [&](const Instruction &Instr) {
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return isModSet(AA.getModRefInfo(&Instr, Loc)) ||
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++NumScanned > MaxInstrsToScan;
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});
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}
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// Combine patterns like:
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// %0 = load <4 x i32>, <4 x i32>* %a
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// %1 = insertelement <4 x i32> %0, i32 %b, i32 1
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// store <4 x i32> %1, <4 x i32>* %a
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// to:
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// %0 = bitcast <4 x i32>* %a to i32*
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// %1 = getelementptr inbounds i32, i32* %0, i64 0, i64 1
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// store i32 %b, i32* %1
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bool VectorCombine::foldSingleElementStore(Instruction &I) {
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StoreInst *SI = dyn_cast<StoreInst>(&I);
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if (!SI || !SI->isSimple() || !SI->getValueOperand()->getType()->isVectorTy())
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return false;
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// TODO: Combine more complicated patterns (multiple insert) by referencing
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// TargetTransformInfo.
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Instruction *Source;
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Value *NewElement, *Idx;
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if (!match(SI->getValueOperand(),
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m_InsertElt(m_Instruction(Source), m_Value(NewElement),
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m_Value(Idx))))
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return false;
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if (auto *Load = dyn_cast<LoadInst>(Source)) {
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const DataLayout &DL = I.getModule()->getDataLayout();
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Value *SrcAddr = Load->getPointerOperand()->stripPointerCasts();
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// Don't optimize for atomic/volatile load or stores.
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if (!Load->isSimple() || Load->getParent() != SI->getParent() ||
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!DL.typeSizeEqualsStoreSize(Load->getType()) ||
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SrcAddr != SI->getPointerOperand()->stripPointerCasts() ||
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isMemModifiedBetween(Load->getIterator(), SI->getIterator(),
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MemoryLocation::get(SI), AA))
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return false;
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Value *GEP = GetElementPtrInst::CreateInBounds(
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SI->getPointerOperand(), {ConstantInt::get(Idx->getType(), 0), Idx});
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Builder.Insert(GEP);
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StoreInst *NSI = Builder.CreateStore(NewElement, GEP);
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NSI->copyMetadata(*SI);
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if (SI->getAlign() < NSI->getAlign())
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NSI->setAlignment(SI->getAlign());
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replaceValue(I, *NSI);
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// Need erasing the store manually.
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I.eraseFromParent();
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return true;
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}
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return false;
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}
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/// This is the entry point for all transforms. Pass manager differences are
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/// handled in the callers of this function.
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bool VectorCombine::run() {
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@ -769,11 +835,8 @@ bool VectorCombine::run() {
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// Ignore unreachable basic blocks.
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if (!DT.isReachableFromEntry(&BB))
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continue;
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// Do not delete instructions under here and invalidate the iterator.
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// Walk the block forwards to enable simple iterative chains of transforms.
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// TODO: It could be more efficient to remove dead instructions
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// iteratively in this loop rather than waiting until the end.
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for (Instruction &I : BB) {
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// Use early increment range so that we can erase instructions in loop.
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for (Instruction &I : make_early_inc_range(BB)) {
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if (isa<DbgInfoIntrinsic>(I))
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continue;
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Builder.SetInsertPoint(&I);
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@ -782,6 +845,7 @@ bool VectorCombine::run() {
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MadeChange |= foldBitcastShuf(I);
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MadeChange |= scalarizeBinopOrCmp(I);
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MadeChange |= foldExtractedCmps(I);
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MadeChange |= foldSingleElementStore(I);
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}
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}
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@ -806,6 +870,7 @@ public:
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.addRequired<TargetTransformInfoWrapperPass>();
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AU.addRequired<AAResultsWrapperPass>();
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AU.setPreservesCFG();
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AU.addPreserved<DominatorTreeWrapperPass>();
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AU.addPreserved<GlobalsAAWrapperPass>();
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@ -819,7 +884,8 @@ public:
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return false;
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auto &TTI = getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
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auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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VectorCombine Combiner(F, TTI, DT);
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auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
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VectorCombine Combiner(F, TTI, DT, AA);
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return Combiner.run();
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}
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};
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@ -840,7 +906,8 @@ PreservedAnalyses VectorCombinePass::run(Function &F,
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FunctionAnalysisManager &FAM) {
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TargetTransformInfo &TTI = FAM.getResult<TargetIRAnalysis>(F);
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DominatorTree &DT = FAM.getResult<DominatorTreeAnalysis>(F);
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VectorCombine Combiner(F, TTI, DT);
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AAResults &AA = FAM.getResult<AAManager>(F);
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VectorCombine Combiner(F, TTI, DT, AA);
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if (!Combiner.run())
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return PreservedAnalyses::all();
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PreservedAnalyses PA;
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@ -248,9 +248,9 @@
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; GCN-O1-NEXT: Combine redundant instructions
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; GCN-O1-NEXT: Simplify the CFG
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; GCN-O1-NEXT: Dominator Tree Construction
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; GCN-O1-NEXT: Optimize scalar/vector ops
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; GCN-O1-NEXT: Basic Alias Analysis (stateless AA impl)
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; GCN-O1-NEXT: Function Alias Analysis Results
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; GCN-O1-NEXT: Optimize scalar/vector ops
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; GCN-O1-NEXT: Natural Loop Information
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; GCN-O1-NEXT: Lazy Branch Probability Analysis
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; GCN-O1-NEXT: Lazy Block Frequency Analysis
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@ -168,10 +168,10 @@
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; CHECK-NEXT: Combine redundant instructions
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; CHECK-NEXT: Demanded bits analysis
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; CHECK-NEXT: Bit-Tracking Dead Code Elimination
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Optimize scalar/vector ops
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Alignment from assumptions
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Optimization Remark Emitter
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; CHECK-NEXT: Combine redundant instructions
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; CHECK-NEXT: Lazy Value Information Analysis
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@ -1,98 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -instcombine < %s | FileCheck %s
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define void @insert_store(<16 x i8>* %q, i8 zeroext %s) {
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; CHECK-LABEL: @insert_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
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; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3
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; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <16 x i8>, <16 x i8>* %q
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%vecins = insertelement <16 x i8> %0, i8 %s, i32 3
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store <16 x i8> %vecins, <16 x i8>* %q
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ret void
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}
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define void @single_shuffle_store(<4 x i32>* %a, i32 %b) {
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; CHECK-LABEL: @single_shuffle_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[A:%.*]], align 16
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[B:%.*]], i32 1
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; CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* [[A]], align 16, !nontemporal !0
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a
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%1 = insertelement <4 x i32> %0, i32 %b, i32 1
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%2 = shufflevector <4 x i32> %0, <4 x i32> %1, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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store <4 x i32> %2, <4 x i32>* %a, !nontemporal !0
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ret void
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}
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define void @volatile_update(<16 x i8>* %q, <16 x i8>* %p, i8 zeroext %s) {
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; CHECK-LABEL: @volatile_update(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
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; CHECK-NEXT: [[VECINS0:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3
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; CHECK-NEXT: store volatile <16 x i8> [[VECINS0]], <16 x i8>* [[Q]], align 16
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; CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* [[P:%.*]], align 16
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; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[S]], i32 1
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; CHECK-NEXT: store <16 x i8> [[VECINS1]], <16 x i8>* [[P]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <16 x i8>, <16 x i8>* %q
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%vecins0 = insertelement <16 x i8> %0, i8 %s, i32 3
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store volatile <16 x i8> %vecins0, <16 x i8>* %q
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%1 = load volatile <16 x i8>, <16 x i8>* %p
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%vecins1 = insertelement <16 x i8> %1, i8 %s, i32 1
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store <16 x i8> %vecins1, <16 x i8>* %p
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ret void
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}
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define void @insert_store_addr_differ(<16 x i8>* %p, <16 x i8>* %q, i8 %s) {
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; CHECK-LABEL: @insert_store_addr_differ(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
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; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
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; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[Q:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%ld = load <16 x i8>, <16 x i8>* %p
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%ins = insertelement <16 x i8> %ld, i8 %s, i32 3
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store <16 x i8> %ins, <16 x i8>* %q
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ret void
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}
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define void @insert_store_mem_modify(<16 x i8>* %p, <16 x i8>* %q, <16 x i8>* noalias %r, i8 %s) {
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; CHECK-LABEL: @insert_store_mem_modify(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
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; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[Q:%.*]], align 16
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; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
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; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16
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; CHECK-NEXT: [[LD2:%.*]] = load <16 x i8>, <16 x i8>* [[Q]], align 16
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; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[R:%.*]], align 16
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; CHECK-NEXT: [[INS2:%.*]] = insertelement <16 x i8> [[LD2]], i8 [[S]], i32 7
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; CHECK-NEXT: store <16 x i8> [[INS2]], <16 x i8>* [[Q]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%ld = load <16 x i8>, <16 x i8>* %p
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store <16 x i8> zeroinitializer, <16 x i8>* %q
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%ins = insertelement <16 x i8> %ld, i8 %s, i32 3
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store <16 x i8> %ins, <16 x i8>* %p
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%ld2 = load <16 x i8>, <16 x i8>* %q
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store <16 x i8> zeroinitializer, <16 x i8>* %r
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%ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7
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store <16 x i8> %ins2, <16 x i8>* %q
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ret void
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}
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!0 = !{}
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305
test/Transforms/VectorCombine/load-insert-store.ll
Normal file
305
test/Transforms/VectorCombine/load-insert-store.ll
Normal file
@ -0,0 +1,305 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -vector-combine -data-layout=e < %s | FileCheck %s
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; RUN: opt -S -vector-combine -data-layout=E < %s | FileCheck %s
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define void @insert_store(<16 x i8>* %q, i8 zeroext %s) {
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; CHECK-LABEL: @insert_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q:%.*]], i32 0, i32 3
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; CHECK-NEXT: store i8 [[S:%.*]], i8* [[TMP0]], align 1
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <16 x i8>, <16 x i8>* %q
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%vecins = insertelement <16 x i8> %0, i8 %s, i32 3
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store <16 x i8> %vecins, <16 x i8>* %q, align 16
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ret void
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}
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define void @insert_store_i16_align1(<8 x i16>* %q, i16 zeroext %s) {
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; CHECK-LABEL: @insert_store_i16_align1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[Q:%.*]], i32 0, i32 3
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; CHECK-NEXT: store i16 [[S:%.*]], i16* [[TMP0]], align 1
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <8 x i16>, <8 x i16>* %q
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%vecins = insertelement <8 x i16> %0, i16 %s, i32 3
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store <8 x i16> %vecins, <8 x i16>* %q, align 1
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ret void
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}
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define void @insert_store_v9i4(<9 x i4>* %q, i4 zeroext %s) {
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; CHECK-LABEL: @insert_store_v9i4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <9 x i4>, <9 x i4>* [[Q:%.*]], align 16
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; CHECK-NEXT: [[VECINS:%.*]] = insertelement <9 x i4> [[TMP0]], i4 [[S:%.*]], i32 3
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; CHECK-NEXT: store <9 x i4> [[VECINS]], <9 x i4>* [[Q]], align 1
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <9 x i4>, <9 x i4>* %q
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%vecins = insertelement <9 x i4> %0, i4 %s, i32 3
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store <9 x i4> %vecins, <9 x i4>* %q, align 1
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ret void
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}
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define void @insert_store_v4i27(<4 x i27>* %q, i27 zeroext %s) {
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; CHECK-LABEL: @insert_store_v4i27(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i27>, <4 x i27>* [[Q:%.*]], align 16
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; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x i27> [[TMP0]], i27 [[S:%.*]], i32 3
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; CHECK-NEXT: store <4 x i27> [[VECINS]], <4 x i27>* [[Q]], align 1
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <4 x i27>, <4 x i27>* %q
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%vecins = insertelement <4 x i27> %0, i27 %s, i32 3
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store <4 x i27> %vecins, <4 x i27>* %q, align 1
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ret void
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}
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define void @insert_store_blk_differ(<8 x i16>* %q, i16 zeroext %s) {
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; CHECK-LABEL: @insert_store_blk_differ(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, <8 x i16>* [[Q:%.*]], align 16
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; CHECK-NEXT: br label [[CONT:%.*]]
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; CHECK: cont:
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; CHECK-NEXT: [[VECINS:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[S:%.*]], i32 3
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; CHECK-NEXT: store <8 x i16> [[VECINS]], <8 x i16>* [[Q]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <8 x i16>, <8 x i16>* %q
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br label %cont
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cont:
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%vecins = insertelement <8 x i16> %0, i16 %s, i32 3
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store <8 x i16> %vecins, <8 x i16>* %q
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ret void
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}
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||||
define void @insert_store_nonconst(<16 x i8>* %q, i8 zeroext %s, i32 %idx) {
|
||||
; CHECK-LABEL: @insert_store_nonconst(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q:%.*]], i32 0, i32 [[IDX:%.*]]
|
||||
; CHECK-NEXT: store i8 [[S:%.*]], i8* [[TMP0]], align 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %q
|
||||
%vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx
|
||||
store <16 x i8> %vecins, <16 x i8>* %q
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @insert_store_ptr_strip(<16 x i8>* %q, i8 zeroext %s, i32 %idx) {
|
||||
; CHECK-LABEL: @insert_store_ptr_strip(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[ADDR0:%.*]] = bitcast <16 x i8>* [[Q:%.*]] to <2 x i64>*
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q]], i32 0, i32 [[IDX:%.*]]
|
||||
; CHECK-NEXT: store i8 [[S:%.*]], i8* [[TMP0]], align 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %q
|
||||
%vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx
|
||||
%addr0 = bitcast <16 x i8>* %q to <2 x i64>*
|
||||
%addr1 = getelementptr <2 x i64>, <2 x i64>* %addr0, i64 0
|
||||
%addr2 = bitcast <2 x i64>* %addr1 to <16 x i8>*
|
||||
store <16 x i8> %vecins, <16 x i8>* %addr2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @volatile_update(<16 x i8>* %q, <16 x i8>* %p, i8 zeroext %s) {
|
||||
; CHECK-LABEL: @volatile_update(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
|
||||
; CHECK-NEXT: [[VECINS0:%.*]] = insertelement <16 x i8> [[TMP0]], i8 [[S:%.*]], i32 3
|
||||
; CHECK-NEXT: store volatile <16 x i8> [[VECINS0]], <16 x i8>* [[Q]], align 16
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* [[P:%.*]], align 16
|
||||
; CHECK-NEXT: [[VECINS1:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[S]], i32 1
|
||||
; CHECK-NEXT: store <16 x i8> [[VECINS1]], <16 x i8>* [[P]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%0 = load <16 x i8>, <16 x i8>* %q
|
||||
%vecins0 = insertelement <16 x i8> %0, i8 %s, i32 3
|
||||
store volatile <16 x i8> %vecins0, <16 x i8>* %q
|
||||
|
||||
%1 = load volatile <16 x i8>, <16 x i8>* %p
|
||||
%vecins1 = insertelement <16 x i8> %1, i8 %s, i32 1
|
||||
store <16 x i8> %vecins1, <16 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @insert_store_addr_differ(<16 x i8>* %p, <16 x i8>* %q, i8 %s) {
|
||||
; CHECK-LABEL: @insert_store_addr_differ(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
|
||||
; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
|
||||
; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[Q:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%ld = load <16 x i8>, <16 x i8>* %p
|
||||
%ins = insertelement <16 x i8> %ld, i8 %s, i32 3
|
||||
store <16 x i8> %ins, <16 x i8>* %q
|
||||
ret void
|
||||
}
|
||||
|
||||
; We can't transform if any instr could modify memory in between.
|
||||
define void @insert_store_mem_modify(<16 x i8>* %p, <16 x i8>* %q, <16 x i8>* noalias %r, i8 %s, i32 %m) {
|
||||
; CHECK-LABEL: @insert_store_mem_modify(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
|
||||
; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[Q:%.*]], align 16
|
||||
; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
|
||||
; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16
|
||||
; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[R:%.*]], align 16
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[Q]], i32 0, i32 7
|
||||
; CHECK-NEXT: store i8 [[S]], i8* [[TMP0]], align 1
|
||||
; CHECK-NEXT: [[PTR0:%.*]] = bitcast <16 x i8>* [[P]] to <4 x i32>*
|
||||
; CHECK-NEXT: [[LD3:%.*]] = load <4 x i32>, <4 x i32>* [[PTR0]], align 16
|
||||
; CHECK-NEXT: store <16 x i8> zeroinitializer, <16 x i8>* [[P]], align 16
|
||||
; CHECK-NEXT: [[INS3:%.*]] = insertelement <4 x i32> [[LD3]], i32 [[M:%.*]], i32 0
|
||||
; CHECK-NEXT: store <4 x i32> [[INS3]], <4 x i32>* [[PTR0]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
; p may alias q
|
||||
%ld = load <16 x i8>, <16 x i8>* %p
|
||||
store <16 x i8> zeroinitializer, <16 x i8>* %q
|
||||
%ins = insertelement <16 x i8> %ld, i8 %s, i32 3
|
||||
store <16 x i8> %ins, <16 x i8>* %p
|
||||
|
||||
; p never aliases r
|
||||
%ld2 = load <16 x i8>, <16 x i8>* %q
|
||||
store <16 x i8> zeroinitializer, <16 x i8>* %r
|
||||
%ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7
|
||||
store <16 x i8> %ins2, <16 x i8>* %q
|
||||
|
||||
; p must alias ptr0
|
||||
%ptr0 = bitcast <16 x i8>* %p to <4 x i32>*
|
||||
%ld3 = load <4 x i32>, <4 x i32>* %ptr0
|
||||
store <16 x i8> zeroinitializer, <16 x i8>* %p
|
||||
%ins3 = insertelement <4 x i32> %ld3, i32 %m, i32 0
|
||||
store <4 x i32> %ins3, <4 x i32>* %ptr0
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check cases when calls may modify memory
|
||||
define void @insert_store_with_call(<16 x i8>* %p, <16 x i8>* %q, i8 %s) {
|
||||
; CHECK-LABEL: @insert_store_with_call(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[LD:%.*]] = load <16 x i8>, <16 x i8>* [[P:%.*]], align 16
|
||||
; CHECK-NEXT: call void @maywrite(<16 x i8>* [[P]])
|
||||
; CHECK-NEXT: [[INS:%.*]] = insertelement <16 x i8> [[LD]], i8 [[S:%.*]], i32 3
|
||||
; CHECK-NEXT: store <16 x i8> [[INS]], <16 x i8>* [[P]], align 16
|
||||
; CHECK-NEXT: call void @foo()
|
||||
; CHECK-NEXT: call void @nowrite(<16 x i8>* [[P]])
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[P]], i32 0, i32 7
|
||||
; CHECK-NEXT: store i8 [[S]], i8* [[TMP0]], align 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%ld = load <16 x i8>, <16 x i8>* %p
|
||||
call void @maywrite(<16 x i8>* %p)
|
||||
%ins = insertelement <16 x i8> %ld, i8 %s, i32 3
|
||||
store <16 x i8> %ins, <16 x i8>* %p
|
||||
call void @foo() ; Barrier
|
||||
%ld2 = load <16 x i8>, <16 x i8>* %p
|
||||
call void @nowrite(<16 x i8>* %p)
|
||||
%ins2 = insertelement <16 x i8> %ld2, i8 %s, i32 7
|
||||
store <16 x i8> %ins2, <16 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo()
|
||||
declare void @maywrite(<16 x i8>*)
|
||||
declare void @nowrite(<16 x i8>*) readonly
|
||||
|
||||
; To test if number of instructions in-between exceeds the limit (default 30),
|
||||
; the combine will quit.
|
||||
define i32 @insert_store_maximum_scan_instrs(i32 %arg, i16* %arg1, <16 x i8>* %arg2, i8 zeroext %arg3) {
|
||||
; CHECK-LABEL: @insert_store_maximum_scan_instrs(
|
||||
; CHECK-NEXT: bb:
|
||||
; CHECK-NEXT: [[I:%.*]] = or i32 [[ARG:%.*]], 1
|
||||
; CHECK-NEXT: [[I4:%.*]] = load <16 x i8>, <16 x i8>* [[ARG2:%.*]], align 16
|
||||
; CHECK-NEXT: [[I5:%.*]] = tail call i32 @bar(i32 [[I]], i1 true)
|
||||
; CHECK-NEXT: [[I6:%.*]] = shl i32 [[ARG]], [[I5]]
|
||||
; CHECK-NEXT: [[I7:%.*]] = lshr i32 [[I6]], 26
|
||||
; CHECK-NEXT: [[I8:%.*]] = trunc i32 [[I7]] to i8
|
||||
; CHECK-NEXT: [[I9:%.*]] = and i8 [[I8]], 31
|
||||
; CHECK-NEXT: [[I10:%.*]] = lshr i32 [[I6]], 11
|
||||
; CHECK-NEXT: [[I11:%.*]] = and i32 [[I10]], 32767
|
||||
; CHECK-NEXT: [[I12:%.*]] = zext i8 [[I9]] to i64
|
||||
; CHECK-NEXT: [[I13:%.*]] = getelementptr inbounds i16, i16* [[ARG1:%.*]], i64 [[I12]]
|
||||
; CHECK-NEXT: [[I14:%.*]] = load i16, i16* [[I13]], align 2
|
||||
; CHECK-NEXT: [[I15:%.*]] = zext i16 [[I14]] to i32
|
||||
; CHECK-NEXT: [[I16:%.*]] = add nuw nsw i8 [[I9]], 1
|
||||
; CHECK-NEXT: [[I17:%.*]] = zext i8 [[I16]] to i64
|
||||
; CHECK-NEXT: [[I18:%.*]] = getelementptr inbounds i16, i16* [[ARG1]], i64 [[I17]]
|
||||
; CHECK-NEXT: [[I19:%.*]] = load i16, i16* [[I18]], align 2
|
||||
; CHECK-NEXT: [[I20:%.*]] = zext i16 [[I19]] to i32
|
||||
; CHECK-NEXT: [[I21:%.*]] = sub nsw i32 [[I20]], [[I15]]
|
||||
; CHECK-NEXT: [[I22:%.*]] = mul nsw i32 [[I11]], [[I21]]
|
||||
; CHECK-NEXT: [[I23:%.*]] = ashr i32 [[I22]], 15
|
||||
; CHECK-NEXT: [[I24:%.*]] = shl nuw nsw i32 [[I5]], 15
|
||||
; CHECK-NEXT: [[I25:%.*]] = xor i32 [[I24]], 1015808
|
||||
; CHECK-NEXT: [[I26:%.*]] = add nuw nsw i32 [[I25]], [[I15]]
|
||||
; CHECK-NEXT: [[I27:%.*]] = add nsw i32 [[I26]], [[I23]]
|
||||
; CHECK-NEXT: [[I28:%.*]] = sitofp i32 [[ARG]] to double
|
||||
; CHECK-NEXT: [[I29:%.*]] = tail call double @llvm.log2.f64(double [[I28]])
|
||||
; CHECK-NEXT: [[I30:%.*]] = fptosi double [[I29]] to i32
|
||||
; CHECK-NEXT: [[I31:%.*]] = shl nsw i32 [[I30]], 15
|
||||
; CHECK-NEXT: [[I32:%.*]] = or i32 [[I31]], 4
|
||||
; CHECK-NEXT: [[I33:%.*]] = icmp eq i32 [[I27]], [[I32]]
|
||||
; CHECK-NEXT: [[I34:%.*]] = select i1 [[I33]], i32 [[ARG]], i32 [[I31]]
|
||||
; CHECK-NEXT: [[I35:%.*]] = lshr i32 [[I34]], 1
|
||||
; CHECK-NEXT: [[I36:%.*]] = insertelement <16 x i8> [[I4]], i8 [[ARG3:%.*]], i32 3
|
||||
; CHECK-NEXT: store <16 x i8> [[I36]], <16 x i8>* [[ARG2]], align 16
|
||||
; CHECK-NEXT: ret i32 [[I35]]
|
||||
;
|
||||
bb:
|
||||
%i = or i32 %arg, 1
|
||||
%i4 = load <16 x i8>, <16 x i8>* %arg2, align 16
|
||||
%i5 = tail call i32 @bar(i32 %i, i1 true)
|
||||
%i6 = shl i32 %arg, %i5
|
||||
%i7 = lshr i32 %i6, 26
|
||||
%i8 = trunc i32 %i7 to i8
|
||||
%i9 = and i8 %i8, 31
|
||||
%i10 = lshr i32 %i6, 11
|
||||
%i11 = and i32 %i10, 32767
|
||||
%i12 = zext i8 %i9 to i64
|
||||
%i13 = getelementptr inbounds i16, i16* %arg1, i64 %i12
|
||||
%i14 = load i16, i16* %i13, align 2
|
||||
%i15 = zext i16 %i14 to i32
|
||||
%i16 = add nuw nsw i8 %i9, 1
|
||||
%i17 = zext i8 %i16 to i64
|
||||
%i18 = getelementptr inbounds i16, i16* %arg1, i64 %i17
|
||||
%i19 = load i16, i16* %i18, align 2
|
||||
%i20 = zext i16 %i19 to i32
|
||||
%i21 = sub nsw i32 %i20, %i15
|
||||
%i22 = mul nsw i32 %i11, %i21
|
||||
%i23 = ashr i32 %i22, 15
|
||||
%i24 = shl nuw nsw i32 %i5, 15
|
||||
%i25 = xor i32 %i24, 1015808
|
||||
%i26 = add nuw nsw i32 %i25, %i15
|
||||
%i27 = add nsw i32 %i26, %i23
|
||||
%i28 = sitofp i32 %arg to double
|
||||
%i29 = tail call double @llvm.log2.f64(double %i28)
|
||||
%i30 = fptosi double %i29 to i32
|
||||
%i31 = shl nsw i32 %i30, 15
|
||||
%i32 = or i32 %i31, 4
|
||||
%i33 = icmp eq i32 %i27, %i32
|
||||
%i34 = select i1 %i33, i32 %arg, i32 %i31
|
||||
%i35 = lshr i32 %i34, 1
|
||||
%i36 = insertelement <16 x i8> %i4, i8 %arg3, i32 3
|
||||
store <16 x i8> %i36, <16 x i8>* %arg2, align 16
|
||||
ret i32 %i35
|
||||
}
|
||||
|
||||
declare i32 @bar(i32, i1) readonly
|
||||
declare double @llvm.log2.f64(double)
|
||||
Loading…
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Reference in New Issue
Block a user