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https://github.com/RPCS3/llvm-mirror.git
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R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16
llvm-svn: 206547
This commit is contained in:
Matt Arsenault
parent
3756e7abc3
commit
42cf57d738
@ -165,6 +165,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::LOAD, MVT::i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
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@ -537,6 +537,8 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
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case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
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case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
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case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
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case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
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case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
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case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
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case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
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case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
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@ -915,8 +917,10 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
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MachineBasicBlock *MBB = Inst->getParent();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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unsigned Opcode = Inst->getOpcode();
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// Handle some special cases
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switch(Inst->getOpcode()) {
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switch (Opcode) {
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case AMDGPU::S_MOV_B64: {
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DebugLoc DL = Inst->getDebugLoc();
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@ -988,26 +992,28 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
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Inst->RemoveOperand(i);
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}
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// Add the implict and explicit register definitions.
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if (NewDesc.ImplicitUses) {
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for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
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unsigned Reg = NewDesc.ImplicitUses[i];
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Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
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}
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if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
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// We are converting these to a BFE, so we need to add the missing
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// operands for the size and offset.
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unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
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Inst->addOperand(MachineOperand::CreateImm(0));
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Inst->addOperand(MachineOperand::CreateImm(Size));
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// XXX - Other pointless operands. There are 4, but it seems you only need
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// 3 to not hit an assertion later in MCInstLower.
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Inst->addOperand(MachineOperand::CreateImm(0));
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Inst->addOperand(MachineOperand::CreateImm(0));
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Inst->addOperand(MachineOperand::CreateImm(0));
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Inst->addOperand(MachineOperand::CreateImm(0));
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}
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if (NewDesc.ImplicitDefs) {
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for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
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unsigned Reg = NewDesc.ImplicitDefs[i];
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Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
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}
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}
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addDescImplicitUseDef(NewDesc, Inst);
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// Update the destination register class.
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const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
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switch (Inst->getOpcode()) {
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switch (Opcode) {
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// For target instructions, getOpRegClass just returns the virtual
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// register class associated with the operand, so we need to find an
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// equivalent VGPR register class in order to move the instruction to the
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@ -1120,6 +1126,24 @@ void SIInstrInfo::splitScalar64BitOp(SmallVectorImpl<MachineInstr *> &Worklist,
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Worklist.push_back(HiHalf);
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}
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void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
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MachineInstr *Inst) const {
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// Add the implict and explicit register definitions.
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if (NewDesc.ImplicitUses) {
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for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
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unsigned Reg = NewDesc.ImplicitUses[i];
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Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
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}
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}
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if (NewDesc.ImplicitDefs) {
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for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
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unsigned Reg = NewDesc.ImplicitDefs[i];
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Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
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}
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}
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}
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MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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@ -47,6 +47,7 @@ private:
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void splitScalar64BitOp(SmallVectorImpl<MachineInstr *> & Worklist,
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MachineInstr *Inst, unsigned Opcode) const;
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void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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@ -68,8 +68,12 @@ def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>;
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//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>;
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def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>;
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//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>;
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//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>;
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//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>;
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def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8",
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[(set i32:$dst, (sext_inreg i32:$src0, i8))]
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>;
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def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16",
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[(set i32:$dst, (sext_inreg i32:$src0, i16))]
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>;
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////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>;
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////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>;
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////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>;
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@ -124,6 +128,21 @@ def S_CMPK_EQ_I32 : SOPK <
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>;
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*/
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// Handle sext_inreg in i64
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def : Pat <
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(i64 (sext_inreg i64:$src, i8)),
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(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(S_SEXT_I32_I8 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
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(S_MOV_B32 -1), sub1)
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>;
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def : Pat <
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(i64 (sext_inreg i64:$src, i16)),
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(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(S_SEXT_I32_I16 (EXTRACT_SUBREG i64:$src, sub0)), sub0),
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(S_MOV_B32 -1), sub1)
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>;
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let isCompare = 1 in {
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def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>;
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def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>;
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@ -21,8 +21,9 @@ define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
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; FUNC-LABEL: @sext_in_reg_i8_to_i32
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
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; SI: BUFFER_STORE_DWORD [[EXTRACT]],
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; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
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; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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@ -38,8 +39,9 @@ define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounw
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; FUNC-LABEL: @sext_in_reg_i16_to_i32
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 16
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; SI: BUFFER_STORE_DWORD [[EXTRACT]],
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; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
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; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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@ -55,8 +57,9 @@ define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) noun
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; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], [[VAL]], 0, 8
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; SI: BUFFER_STORE_DWORD [[EXTRACT]],
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; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
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; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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@ -71,9 +74,10 @@ define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a,
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}
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; FUNC-LABEL: @sext_in_reg_i8_to_i64
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
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; SI: BUFFER_STORE_DWORD
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: S_MOV_B32 {{s[0-9]+}}, -1
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
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@ -94,9 +98,10 @@ define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw
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}
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; FUNC-LABEL: @sext_in_reg_i16_to_i64
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 16
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; SI: V_ASHRREV_I32_e32 {{v[0-9]+}}, 31,
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; SI: BUFFER_STORE_DWORD
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: S_MOV_B32 {{s[0-9]+}}, -1
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
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@ -237,8 +242,8 @@ define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %
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}
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; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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@ -254,10 +259,10 @@ define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %
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}
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; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: BUFFER_STORE_DWORDX4
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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@ -275,8 +280,8 @@ define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %
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}
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; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: V_BFE_I32 {{v[0-9]+}}, {{s[0-9]+}}, 0, 8
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; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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@ -285,8 +290,8 @@ define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
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%c = add <2 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <2 x i32> %c, <i32 24, i32 24>
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%ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
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%shl = shl <2 x i32> %c, <i32 16, i32 16>
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%ashr = ashr <2 x i32> %shl, <i32 16, i32 16>
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store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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