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[mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6

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There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink
tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly
selects the `JALRC16` compact 2-byte instruction which takes a target
instruction address from a register only and assign `R_MIPS_32` relocation
for this instruction. This relocation completely overwrites `JALRC16`
and nearby instructions.

This patch adds missed matching patterns, selects `BALC` instruction and
assign a correct `R_MICROMIPS_PC26_S1` relocation.

Differential Revision: https://reviews.llvm.org/D64552

llvm-svn: 365870
This commit is contained in:
Simon Atanasyan 2019-07-12 04:58:45 +00:00
parent 1bbd63ef60
commit 42e0928a60
6 changed files with 39 additions and 16 deletions
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13
lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -1774,6 +1774,19 @@ let AddedComplexity = 41 in {
def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
}
let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
PseudoInstExpansion<(JumpInst Opnd:$target)>;
}
def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
(JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
(JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
def TAILCALLREG_MMR6 : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;

2
lib/Target/Mips/MipsScheduleGeneric.td
View File

@ -384,7 +384,7 @@ def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6,
BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6,
BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6,
BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6,
BOVC_MMR6, DERET_MMR6, ERETNC_MMR6,
BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6,
ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM,
JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6,
B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>;

4
test/CodeGen/Mips/llvm-ir/fptosi.ll
View File

@ -208,7 +208,7 @@ define i32 @test1(float %t) {
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4
; MMR6-SF-NEXT: jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
@ -399,7 +399,7 @@ define i32 @test2(double %t) {
; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
; MMR6-SF-NEXT: # <MCOperand Imm:20>>
; MMR6-SF-NEXT: .cfi_offset 31, -4
; MMR6-SF-NEXT: jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW

2
test/CodeGen/Mips/micromips-delay-slot.ll
View File

@ -18,5 +18,5 @@ declare i32 @bar(i32 signext) #1
; CHECK: jals
; CHECK-NEXT: sll16
; CHECK-MMR6: jal
; CHECK-MMR6: balc
; CHECK-MMR6-NOT: sll16

16
test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll
View File

@ -1,13 +1,23 @@
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
; RUN: -stop-after=finalize-isel < %s | FileCheck --check-prefix=MM2 %s
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r6 -mattr=+micromips \
; RUN: -stop-after=finalize-isel < %s | FileCheck --check-prefix=MM6 %s
; CHECK: JAL_MM
; CHECK-NOT: JALR16_MM
; MM2: JAL_MM @bar
; MM2: JAL_MM &memset
; MM2-NOT: JALR16_MM
; MM6: JAL_MMR6 @bar
; MM6: JAL_MMR6 &memset
; MM6-NOT: JALRC16_MMR6
define dso_local void @foo(i32* nocapture %ar) local_unnamed_addr {
entry:
call void @bar()
%0 = bitcast i32* %ar to i8*
tail call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 100, i1 false)
ret void
}
declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1)
declare void @bar()

18
test/CodeGen/Mips/tailcall/tailcall.ll
View File

@ -47,7 +47,7 @@ entry:
; PIC32MM: jalr $25
; PIC32R6: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; N64: jalr $25
; N64R6: jalr $25
; PIC16: jalrc
@ -65,7 +65,7 @@ entry:
; PIC32MM: jalr $25
; PIC32R6: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; N64: jalr $25
; N64R6: jalr $25
; PIC16: jalrc
@ -83,7 +83,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; N64: jalr $25
; N64R6: jalr $25
; PIC16: jalrc
@ -179,7 +179,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; PIC64: jalr $25
; STATIC64: jal
; PIC16: jalrc
@ -217,7 +217,7 @@ entry:
; PIC32R6: jalrc $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalrc $25
@ -236,7 +236,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalr $25
@ -255,7 +255,7 @@ entry:
; PIC32R6: jalrc $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalrc $25
@ -276,7 +276,7 @@ entry:
; PIC32R6: jalrc $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; STATIC64: jal
; PIC64: jalr $25
; PIC64R6: jalrc $25
@ -297,7 +297,7 @@ entry:
; PIC32R6: jalr $25
; PIC32MM: jalr $25
; STATIC32: jal
; STATIC32MMR6: jal
; STATIC32MMR6: balc
; STATIC64: jal
; PIC64R6: jalr $25
; PIC64: jalr $25