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[GlobalISel] Pass MachineOperands into MachineIRBuilder helper methods
Reviewers: arsenm, aditya_nandakumar, aemerson Subscribers: wdng, rovka, hiraditya, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72849
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@ -687,7 +687,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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SmallVector<Register, 4> Srcs = {SrcReg};
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for (unsigned Part = 1; Part < NumParts; ++Part)
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Srcs.push_back(PadReg);
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
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MIRBuilder.buildMerge(MI.getOperand(0), Srcs);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -701,8 +701,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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return UnableToLegalize;
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}
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auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
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MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
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auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
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MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0));
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MI.eraseFromParent();
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return Legalized;
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}
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@ -770,7 +770,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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DstRegs.push_back(DstReg);
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BorrowIn = BorrowOut;
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -791,7 +791,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
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Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
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auto &MMO = **MI.memoperands_begin();
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MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
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MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO);
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MIRBuilder.buildAnyExt(DstReg, TmpReg);
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MI.eraseFromParent();
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return Legalized;
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@ -839,7 +839,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
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auto &MMO = **MI.memoperands_begin();
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MIRBuilder.buildTrunc(TmpReg, SrcReg);
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MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
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MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -917,7 +917,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
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}
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MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
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Observer.changedInstr(MI);
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MI.eraseFromParent();
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return Legalized;
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@ -941,11 +941,11 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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Observer.changingInstr(MI);
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Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
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Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
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MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2));
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Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
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Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
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MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3));
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CmpInst::Predicate Pred =
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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@ -956,14 +956,14 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
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MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
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MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
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MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
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MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero);
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} else {
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MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
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MachineInstrBuilder CmpHEQ =
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MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
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MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
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ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
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MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
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MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH);
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}
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Observer.changedInstr(MI);
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MI.eraseFromParent();
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@ -984,13 +984,13 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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// We don't lose any non-extension bits by truncating the src and
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// sign-extending the dst.
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MachineOperand &MO1 = MI.getOperand(1);
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auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
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auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
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MO1.setReg(TruncMIB->getOperand(0).getReg());
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MachineOperand &MO2 = MI.getOperand(0);
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Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
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MIRBuilder.buildSExt(MO2.getReg(), DstExt);
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MIRBuilder.buildSExt(MO2, DstExt);
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MO2.setReg(DstExt);
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Observer.changedInstr(MI);
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return Legalized;
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@ -1017,7 +1017,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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}
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// Explode the big arguments into smaller chunks.
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MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
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MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1));
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Register AshrCstReg =
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MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
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@ -1076,7 +1076,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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DstRegs.push_back(DstPart.getReg(0));
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
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MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
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Observer.changedInstr(MI);
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MI.eraseFromParent();
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@ -1088,14 +1088,14 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
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unsigned OpIdx, unsigned ExtOpcode) {
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MachineOperand &MO = MI.getOperand(OpIdx);
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auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
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auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
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MO.setReg(ExtB->getOperand(0).getReg());
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}
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void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
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unsigned OpIdx) {
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MachineOperand &MO = MI.getOperand(OpIdx);
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auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO.getReg());
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auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
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MO.setReg(ExtB->getOperand(0).getReg());
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}
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@ -1104,7 +1104,7 @@ void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
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MachineOperand &MO = MI.getOperand(OpIdx);
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Register DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
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MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
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MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
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MO.setReg(DstExt);
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}
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@ -1113,7 +1113,7 @@ void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
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MachineOperand &MO = MI.getOperand(OpIdx);
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Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
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MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
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MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
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MO.setReg(DstTrunc);
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}
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@ -1122,7 +1122,7 @@ void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
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MachineOperand &MO = MI.getOperand(OpIdx);
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Register DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
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MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
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MIRBuilder.buildExtract(MO, DstExt, 0);
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MO.setReg(DstExt);
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}
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@ -1428,8 +1428,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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case TargetOpcode::G_USUBO: {
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if (TypeIdx == 1)
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return UnableToLegalize; // TODO
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auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2).getReg());
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auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3).getReg());
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auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
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auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
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unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
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? TargetOpcode::G_ADD
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: TargetOpcode::G_SUB;
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@ -1440,10 +1440,9 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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auto AndOp = MIRBuilder.buildAnd(
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WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue()));
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// There is no overflow if the AndOp is the same as NewOp.
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MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
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AndOp);
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MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
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// Now trunc the NewOp to the original result.
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MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
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MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -1958,14 +1957,12 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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case TargetOpcode::G_SREM:
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case TargetOpcode::G_UREM: {
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Register QuotReg = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildInstr(
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MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg},
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{MI.getOperand(1).getReg(), MI.getOperand(2).getReg()});
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MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg},
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{MI.getOperand(1), MI.getOperand(2)});
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Register ProdReg = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
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MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
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ProdReg);
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MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2));
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MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), ProdReg);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -2310,8 +2307,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
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auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
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MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0).getReg());
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MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0).getReg());
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MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
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MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
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MI.eraseFromParent();
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return Legalized;
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}
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@ -2390,7 +2387,7 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
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SmallVector<SrcOp, 4> SrcOps;
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
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Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
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MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I), Offset);
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SrcOps.push_back(PartOpReg);
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}
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@ -2406,8 +2403,7 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
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SmallVector<SrcOp, 4> SrcOps;
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
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Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
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MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
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BitsForNumParts);
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MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I), BitsForNumParts);
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SrcOps.push_back(PartOpReg);
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}
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@ -3096,10 +3092,10 @@ LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
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Register InL = MRI.createGenericVirtualRegister(HalfTy);
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Register InH = MRI.createGenericVirtualRegister(HalfTy);
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MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
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MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
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if (Amt.isNullValue()) {
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
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MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
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MI.eraseFromParent();
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return Legalized;
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}
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@ -3172,7 +3168,7 @@ LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
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}
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}
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
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MIRBuilder.buildMerge(MI.getOperand(0), {Lo.getReg(), Hi.getReg()});
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MI.eraseFromParent();
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return Legalized;
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@ -3220,7 +3216,7 @@ LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
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Register InL = MRI.createGenericVirtualRegister(HalfTy);
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Register InH = MRI.createGenericVirtualRegister(HalfTy);
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MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
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MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
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auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
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auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
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@ -3757,8 +3753,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
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auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
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SrcReg, MIBZero);
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MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
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MIBCtlzZU);
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MIRBuilder.buildSelect(MI.getOperand(0), MIBICmp, MIBLen, MIBCtlzZU);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -3782,8 +3777,8 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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Op = MIBOp->getOperand(0).getReg();
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}
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auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op);
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MIRBuilder.buildSub(MI.getOperand(0).getReg(),
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MIRBuilder.buildConstant(Ty, Len), MIBPop);
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MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(Ty, Len),
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MIBPop);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -3805,8 +3800,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
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auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
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SrcReg, MIBZero);
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MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
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MIBCttzZU);
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MIRBuilder.buildSelect(MI.getOperand(0), MIBICmp, MIBLen, MIBCttzZU);
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MI.eraseFromParent();
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return Legalized;
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}
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@ -3821,7 +3815,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
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isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
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auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
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MIRBuilder.buildSub(MI.getOperand(0).getReg(), MIBCstLen,
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MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
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MIRBuilder.buildCTLZ(Ty, MIBTmp));
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MI.eraseFromParent();
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return Legalized;
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@ -2005,9 +2005,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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// Add and set the set condition flag.
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unsigned AddsOpc = OpSize == 32 ? AArch64::ADDSWrr : AArch64::ADDSXrr;
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MachineIRBuilder MIRBuilder(I);
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auto AddsMI = MIRBuilder.buildInstr(
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AddsOpc, {I.getOperand(0).getReg()},
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{I.getOperand(2).getReg(), I.getOperand(3).getReg()});
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auto AddsMI = MIRBuilder.buildInstr(AddsOpc, {I.getOperand(0)},
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{I.getOperand(2), I.getOperand(3)});
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constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI);
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// Now, put the overflow result in the register given by the first operand
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@ -3248,7 +3247,7 @@ AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
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bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
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auto ImmFns = selectArithImmed(RHS);
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS.getReg()});
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auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS});
|
||||
|
||||
// If we matched a valid constant immediate, add those operands.
|
||||
if (ImmFns) {
|
||||
@ -3274,7 +3273,7 @@ AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
|
||||
unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
|
||||
Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
|
||||
|
||||
auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()});
|
||||
auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS});
|
||||
|
||||
// If we matched a valid constant immediate, add those operands.
|
||||
if (ImmFns) {
|
||||
@ -3852,9 +3851,8 @@ bool AArch64InstructionSelector::selectShuffleVector(
|
||||
.addUse(Src2Reg)
|
||||
.addImm(AArch64::qsub1);
|
||||
|
||||
auto TBL2 =
|
||||
MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},
|
||||
{RegSeq, IndexLoad->getOperand(0).getReg()});
|
||||
auto TBL2 = MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0)},
|
||||
{RegSeq, IndexLoad->getOperand(0)});
|
||||
constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
|
||||
constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
|
||||
I.eraseFromParent();
|
||||
|
@ -710,10 +710,10 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
|
||||
auto &MMO = **MI.memoperands_begin();
|
||||
if (MI.getOpcode() == TargetOpcode::G_STORE) {
|
||||
auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg});
|
||||
MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1).getReg(), MMO);
|
||||
MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO);
|
||||
} else {
|
||||
Register NewReg = MRI.createGenericVirtualRegister(NewTy);
|
||||
auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1).getReg(), MMO);
|
||||
auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1), MMO);
|
||||
MIRBuilder.buildBitcast({ValReg}, {NewLoad});
|
||||
}
|
||||
MI.eraseFromParent();
|
||||
|
@ -462,7 +462,7 @@ bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
|
||||
// Convert to integer constants, while preserving the binary representation.
|
||||
auto AsInteger =
|
||||
MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
|
||||
MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
|
||||
MIRBuilder.buildConstant(MI.getOperand(0),
|
||||
*ConstantInt::get(Ctx, AsInteger));
|
||||
break;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user