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[GlobalISel] Pass MachineOperands into MachineIRBuilder helper methods

Browse Source 
Reviewers: arsenm, aditya_nandakumar, aemerson

Subscribers: wdng, rovka, hiraditya, volkan, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72849
This commit is contained in:
Jay Foad 2020-01-16 12:37:00 +00:00
parent be9f6d7d6e
commit 43278bacb4
4 changed files with 50 additions and 58 deletions
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88
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -687,7 +687,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
SmallVector<Register, 4> Srcs = {SrcReg}; SmallVector<Register, 4> Srcs = {SrcReg};
for (unsigned Part = 1; Part < NumParts; ++Part) for (unsigned Part = 1; Part < NumParts; ++Part)
Srcs.push_back(PadReg); Srcs.push_back(PadReg);
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs); MIRBuilder.buildMerge(MI.getOperand(0), Srcs);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -701,8 +701,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
return UnableToLegalize; return UnableToLegalize;
} }
auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg()); auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0)); MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0));
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -770,7 +770,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
DstRegs.push_back(DstReg); DstRegs.push_back(DstReg);
BorrowIn = BorrowOut; BorrowIn = BorrowOut;
} }
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -791,7 +791,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
if (8 * MMO.getSize() != DstTy.getSizeInBits()) { if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
auto &MMO = **MI.memoperands_begin(); auto &MMO = **MI.memoperands_begin();
MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO); MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO);
MIRBuilder.buildAnyExt(DstReg, TmpReg); MIRBuilder.buildAnyExt(DstReg, TmpReg);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
@ -839,7 +839,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
auto &MMO = **MI.memoperands_begin(); auto &MMO = **MI.memoperands_begin();
MIRBuilder.buildTrunc(TmpReg, SrcReg); MIRBuilder.buildTrunc(TmpReg, SrcReg);
MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO); MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -917,7 +917,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
} }
MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
Observer.changedInstr(MI); Observer.changedInstr(MI);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
@ -941,11 +941,11 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
Observer.changingInstr(MI); Observer.changingInstr(MI);
Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg()); MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2));
Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg()); MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3));
CmpInst::Predicate Pred = CmpInst::Predicate Pred =
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
@ -956,14 +956,14 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero); MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero);
} else { } else {
MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
MachineInstrBuilder CmpHEQ = MachineInstrBuilder CmpHEQ =
MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH); MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH);
} }
Observer.changedInstr(MI); Observer.changedInstr(MI);
MI.eraseFromParent(); MI.eraseFromParent();
@ -984,13 +984,13 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
// We don't lose any non-extension bits by truncating the src and // We don't lose any non-extension bits by truncating the src and
// sign-extending the dst. // sign-extending the dst.
MachineOperand &MO1 = MI.getOperand(1); MachineOperand &MO1 = MI.getOperand(1);
auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg()); auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
MO1.setReg(TruncMIB->getOperand(0).getReg()); MO1.setReg(TruncMIB->getOperand(0).getReg());
MachineOperand &MO2 = MI.getOperand(0); MachineOperand &MO2 = MI.getOperand(0);
Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
MIRBuilder.buildSExt(MO2.getReg(), DstExt); MIRBuilder.buildSExt(MO2, DstExt);
MO2.setReg(DstExt); MO2.setReg(DstExt);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
@ -1017,7 +1017,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
} }
// Explode the big arguments into smaller chunks. // Explode the big arguments into smaller chunks.
MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg()); MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1));
Register AshrCstReg = Register AshrCstReg =
MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
@ -1076,7 +1076,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
DstRegs.push_back(DstPart.getReg(0)); DstRegs.push_back(DstPart.getReg(0));
} }
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
Observer.changedInstr(MI); Observer.changedInstr(MI);
MI.eraseFromParent(); MI.eraseFromParent();
@ -1088,14 +1088,14 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
unsigned OpIdx, unsigned ExtOpcode) { unsigned OpIdx, unsigned ExtOpcode) {
MachineOperand &MO = MI.getOperand(OpIdx); MachineOperand &MO = MI.getOperand(OpIdx);
auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()}); auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
MO.setReg(ExtB->getOperand(0).getReg()); MO.setReg(ExtB->getOperand(0).getReg());
} }
void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
unsigned OpIdx) { unsigned OpIdx) {
MachineOperand &MO = MI.getOperand(OpIdx); MachineOperand &MO = MI.getOperand(OpIdx);
auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO.getReg()); auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
MO.setReg(ExtB->getOperand(0).getReg()); MO.setReg(ExtB->getOperand(0).getReg());
} }
@ -1104,7 +1104,7 @@ void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
MachineOperand &MO = MI.getOperand(OpIdx); MachineOperand &MO = MI.getOperand(OpIdx);
Register DstExt = MRI.createGenericVirtualRegister(WideTy); Register DstExt = MRI.createGenericVirtualRegister(WideTy);
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt}); MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
MO.setReg(DstExt); MO.setReg(DstExt);
} }
@ -1113,7 +1113,7 @@ void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
MachineOperand &MO = MI.getOperand(OpIdx); MachineOperand &MO = MI.getOperand(OpIdx);
Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc}); MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
MO.setReg(DstTrunc); MO.setReg(DstTrunc);
} }
@ -1122,7 +1122,7 @@ void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
MachineOperand &MO = MI.getOperand(OpIdx); MachineOperand &MO = MI.getOperand(OpIdx);
Register DstExt = MRI.createGenericVirtualRegister(WideTy); Register DstExt = MRI.createGenericVirtualRegister(WideTy);
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
MIRBuilder.buildExtract(MO.getReg(), DstExt, 0); MIRBuilder.buildExtract(MO, DstExt, 0);
MO.setReg(DstExt); MO.setReg(DstExt);
} }
@ -1428,8 +1428,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_USUBO: { case TargetOpcode::G_USUBO: {
if (TypeIdx == 1) if (TypeIdx == 1)
return UnableToLegalize; // TODO return UnableToLegalize; // TODO
auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2).getReg()); auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3).getReg()); auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
? TargetOpcode::G_ADD ? TargetOpcode::G_ADD
: TargetOpcode::G_SUB; : TargetOpcode::G_SUB;
@ -1440,10 +1440,9 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
auto AndOp = MIRBuilder.buildAnd( auto AndOp = MIRBuilder.buildAnd(
WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())); WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue()));
// There is no overflow if the AndOp is the same as NewOp. // There is no overflow if the AndOp is the same as NewOp.
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp, MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
AndOp);
// Now trunc the NewOp to the original result. // Now trunc the NewOp to the original result.
MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp); MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -1958,14 +1957,12 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
case TargetOpcode::G_SREM: case TargetOpcode::G_SREM:
case TargetOpcode::G_UREM: { case TargetOpcode::G_UREM: {
Register QuotReg = MRI.createGenericVirtualRegister(Ty); Register QuotReg = MRI.createGenericVirtualRegister(Ty);
MIRBuilder.buildInstr( MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg},
MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg}, {MI.getOperand(1), MI.getOperand(2)});
{MI.getOperand(1).getReg(), MI.getOperand(2).getReg()});
Register ProdReg = MRI.createGenericVirtualRegister(Ty); Register ProdReg = MRI.createGenericVirtualRegister(Ty);
MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg()); MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2));
MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), ProdReg);
ProdReg);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -2310,8 +2307,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
Register TmpRes = MRI.createGenericVirtualRegister(DstTy); Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0).getReg()); MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0).getReg()); MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -2390,7 +2387,7 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
SmallVector<SrcOp, 4> SrcOps; SmallVector<SrcOp, 4> SrcOps;
for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy); Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset); MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I), Offset);
SrcOps.push_back(PartOpReg); SrcOps.push_back(PartOpReg);
} }
@ -2406,8 +2403,7 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
SmallVector<SrcOp, 4> SrcOps; SmallVector<SrcOp, 4> SrcOps;
for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
Register PartOpReg = MRI.createGenericVirtualRegister(EltTy); Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I), BitsForNumParts);
BitsForNumParts);
SrcOps.push_back(PartOpReg); SrcOps.push_back(PartOpReg);
} }
@ -3096,10 +3092,10 @@ LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
Register InL = MRI.createGenericVirtualRegister(HalfTy); Register InL = MRI.createGenericVirtualRegister(HalfTy);
Register InH = MRI.createGenericVirtualRegister(HalfTy); Register InH = MRI.createGenericVirtualRegister(HalfTy);
MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg()); MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
if (Amt.isNullValue()) { if (Amt.isNullValue()) {
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH}); MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -3172,7 +3168,7 @@ LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
} }
} }
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()}); MIRBuilder.buildMerge(MI.getOperand(0), {Lo.getReg(), Hi.getReg()});
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
@ -3220,7 +3216,7 @@ LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
Register InL = MRI.createGenericVirtualRegister(HalfTy); Register InL = MRI.createGenericVirtualRegister(HalfTy);
Register InH = MRI.createGenericVirtualRegister(HalfTy); Register InH = MRI.createGenericVirtualRegister(HalfTy);
MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg()); MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
@ -3757,8 +3753,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
SrcReg, MIBZero); SrcReg, MIBZero);
MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen, MIRBuilder.buildSelect(MI.getOperand(0), MIBICmp, MIBLen, MIBCtlzZU);
MIBCtlzZU);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -3782,8 +3777,8 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
Op = MIBOp->getOperand(0).getReg(); Op = MIBOp->getOperand(0).getReg();
} }
auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op); auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op);
MIRBuilder.buildSub(MI.getOperand(0).getReg(), MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(Ty, Len),
MIRBuilder.buildConstant(Ty, Len), MIBPop); MIBPop);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -3805,8 +3800,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
SrcReg, MIBZero); SrcReg, MIBZero);
MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen, MIRBuilder.buildSelect(MI.getOperand(0), MIBICmp, MIBLen, MIBCttzZU);
MIBCttzZU);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
@ -3821,7 +3815,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) && if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) { isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len); auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
MIRBuilder.buildSub(MI.getOperand(0).getReg(), MIBCstLen, MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
MIRBuilder.buildCTLZ(Ty, MIBTmp)); MIRBuilder.buildCTLZ(Ty, MIBTmp));
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;

14
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -2005,9 +2005,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
// Add and set the set condition flag. // Add and set the set condition flag.
unsigned AddsOpc = OpSize == 32 ? AArch64::ADDSWrr : AArch64::ADDSXrr; unsigned AddsOpc = OpSize == 32 ? AArch64::ADDSWrr : AArch64::ADDSXrr;
MachineIRBuilder MIRBuilder(I); MachineIRBuilder MIRBuilder(I);
auto AddsMI = MIRBuilder.buildInstr( auto AddsMI = MIRBuilder.buildInstr(AddsOpc, {I.getOperand(0)},
AddsOpc, {I.getOperand(0).getReg()}, {I.getOperand(2), I.getOperand(3)});
{I.getOperand(2).getReg(), I.getOperand(3).getReg()});
constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI); constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI);
// Now, put the overflow result in the register given by the first operand // Now, put the overflow result in the register given by the first operand
@ -3248,7 +3247,7 @@ AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32; bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
auto ImmFns = selectArithImmed(RHS); auto ImmFns = selectArithImmed(RHS);
unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()]; unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS.getReg()}); auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS});
// If we matched a valid constant immediate, add those operands. // If we matched a valid constant immediate, add those operands.
if (ImmFns) { if (ImmFns) {
@ -3274,7 +3273,7 @@ AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()]; unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()}); auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS});
// If we matched a valid constant immediate, add those operands. // If we matched a valid constant immediate, add those operands.
if (ImmFns) { if (ImmFns) {
@ -3852,9 +3851,8 @@ bool AArch64InstructionSelector::selectShuffleVector(
.addUse(Src2Reg) .addUse(Src2Reg)
.addImm(AArch64::qsub1); .addImm(AArch64::qsub1);
auto TBL2 = auto TBL2 = MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0)},
MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()}, {RegSeq, IndexLoad->getOperand(0)});
{RegSeq, IndexLoad->getOperand(0).getReg()});
constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI); constrainSelectedInstRegOperands(*RegSeq, TII, TRI, RBI);
constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI); constrainSelectedInstRegOperands(*TBL2, TII, TRI, RBI);
I.eraseFromParent(); I.eraseFromParent();

4
lib/Target/AArch64/AArch64LegalizerInfo.cpp
View File

@ -710,10 +710,10 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
auto &MMO = **MI.memoperands_begin(); auto &MMO = **MI.memoperands_begin();
if (MI.getOpcode() == TargetOpcode::G_STORE) { if (MI.getOpcode() == TargetOpcode::G_STORE) {
auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg}); auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg});
MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1).getReg(), MMO); MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO);
} else { } else {
Register NewReg = MRI.createGenericVirtualRegister(NewTy); Register NewReg = MRI.createGenericVirtualRegister(NewTy);
auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1).getReg(), MMO); auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1), MMO);
MIRBuilder.buildBitcast({ValReg}, {NewLoad}); MIRBuilder.buildBitcast({ValReg}, {NewLoad});
} }
MI.eraseFromParent(); MI.eraseFromParent();

2
lib/Target/ARM/ARMLegalizerInfo.cpp
View File

@ -462,7 +462,7 @@ bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
// Convert to integer constants, while preserving the binary representation. // Convert to integer constants, while preserving the binary representation.
auto AsInteger = auto AsInteger =
MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt(); MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
MIRBuilder.buildConstant(MI.getOperand(0).getReg(), MIRBuilder.buildConstant(MI.getOperand(0),
*ConstantInt::get(Ctx, AsInteger)); *ConstantInt::get(Ctx, AsInteger));
break; break;
} }