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[Machine Combiner] Refactor machine reassociation code to be target-independent.
No functional change intended. Patch by Haicheng Wu <haicheng@codeaurora.org>! http://reviews.llvm.org/D12887 PR24522 llvm-svn: 248164
This commit is contained in:
Chad Rosier
parent
cfadb3d603
commit
432f88b93e
@ -22,7 +22,29 @@ namespace llvm {
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///
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namespace MachineCombinerPattern {
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// Forward declaration
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enum MC_PATTERN : int;
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enum MC_PATTERN : int {
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// These are commutative variants for reassociating a computation chain. See
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// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
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MC_REASSOC_AX_BY = 0,
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MC_REASSOC_AX_YB = 1,
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MC_REASSOC_XA_BY = 2,
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MC_REASSOC_XA_YB = 3,
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/// Enumeration of instruction pattern supported by AArch64 machine combiner
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MC_NONE,
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MC_MULADDW_OP1,
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MC_MULADDW_OP2,
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MC_MULSUBW_OP1,
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MC_MULSUBW_OP2,
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MC_MULADDWI_OP1,
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MC_MULSUBWI_OP1,
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MC_MULADDX_OP1,
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MC_MULADDX_OP2,
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MC_MULSUBX_OP1,
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MC_MULSUBX_OP2,
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MC_MULADDXI_OP1,
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MC_MULSUBXI_OP1
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};
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} // end namespace MachineCombinerPattern
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} // end namespace llvm
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@ -727,10 +727,27 @@ public:
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/// \param Pattern - Vector of possible combination patterns
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virtual bool getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const {
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const;
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/// Return true if the input \P Inst is part of a chain of dependent ops
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/// that are suitable for reassociation, otherwise return false.
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/// If the instruction's operands must be commuted to have a previous
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/// instruction of the same type define the first source operand, \P Commuted
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/// will be set to true.
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bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
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/// Return true when \P Inst is both associative and commutative.
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virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
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return false;
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}
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/// Return true when \P Inst has reassociable operands in the same \P MBB.
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virtual bool hasReassociableOperands(const MachineInstr &Inst,
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const MachineBasicBlock *MBB) const;
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/// Return true when \P Inst has reassociable sibling.
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bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
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/// When getMachineCombinerPatterns() finds patterns, this function generates
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/// the instructions that could replace the original code sequence. The client
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/// has to decide whether the actual replacement is beneficial or not.
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@ -745,9 +762,23 @@ public:
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MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
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/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
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/// reduce critical path length.
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void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
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MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
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/// This is an architecture-specific helper function of reassociateOps.
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/// Set special operand attributes for new instructions after reassociation.
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virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
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MachineInstr &NewMI1,
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MachineInstr &NewMI2) const {
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return;
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}
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};
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/// Return true when a target supports MachineCombiner.
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virtual bool useMachineCombiner() const { return false; }
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@ -511,6 +511,216 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
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return --Pos;
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}
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bool TargetInstrInfo::hasReassociableOperands(
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const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
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const MachineOperand &Op1 = Inst.getOperand(1);
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const MachineOperand &Op2 = Inst.getOperand(2);
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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// We need virtual register definitions for the operands that we will
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// reassociate.
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MachineInstr *MI1 = nullptr;
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MachineInstr *MI2 = nullptr;
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if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
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MI1 = MRI.getUniqueVRegDef(Op1.getReg());
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if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
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MI2 = MRI.getUniqueVRegDef(Op2.getReg());
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// And they need to be in the trace (otherwise, they won't have a depth).
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if (MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB)
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return true;
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return false;
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}
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bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
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bool &Commuted) const {
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const MachineBasicBlock *MBB = Inst.getParent();
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
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MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
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unsigned AssocOpcode = Inst.getOpcode();
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// If only one operand has the same opcode and it's the second source operand,
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// the operands must be commuted.
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Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
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if (Commuted)
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std::swap(MI1, MI2);
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// 1. The previous instruction must be the same type as Inst.
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// 2. The previous instruction must have virtual register definitions for its
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// operands in the same basic block as Inst.
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// 3. The previous instruction's result must only be used by Inst.
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if (MI1->getOpcode() == AssocOpcode && hasReassociableOperands(*MI1, MBB) &&
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MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()))
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return true;
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return false;
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}
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// 1. The operation must be associative and commutative.
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// 2. The instruction must have virtual register definitions for its
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// operands in the same basic block.
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// 3. The instruction must have a reassociable sibling.
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bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
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bool &Commuted) const {
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if (isAssociativeAndCommutative(Inst) &&
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hasReassociableOperands(Inst, Inst.getParent()) &&
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hasReassociableSibling(Inst, Commuted))
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return true;
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return false;
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}
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// The concept of the reassociation pass is that these operations can benefit
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// from this kind of transformation:
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//
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// A = ? op ?
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// B = A op X (Prev)
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// C = B op Y (Root)
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// -->
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// A = ? op ?
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// B = X op Y
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// C = A op B
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//
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// breaking the dependency between A and B, allowing them to be executed in
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// parallel (or back-to-back in a pipeline) instead of depending on each other.
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// FIXME: This has the potential to be expensive (compile time) while not
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// improving the code at all. Some ways to limit the overhead:
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// 1. Track successful transforms; bail out if hit rate gets too low.
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// 2. Only enable at -O3 or some other non-default optimization level.
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// 3. Pre-screen pattern candidates here: if an operand of the previous
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// instruction is known to not increase the critical path, then don't match
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// that pattern.
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bool TargetInstrInfo::getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
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bool Commute;
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if (isReassociationCandidate(Root, Commute)) {
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// We found a sequence of instructions that may be suitable for a
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// reassociation of operands to increase ILP. Specify each commutation
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// possibility for the Prev instruction in the sequence and let the
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// machine combiner decide if changing the operands is worthwhile.
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if (Commute) {
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_YB);
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_YB);
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} else {
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_BY);
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_BY);
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}
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return true;
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}
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return false;
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}
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/// Attempt the reassociation transformation to reduce critical path length.
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/// See the above comments before getMachineCombinerPatterns().
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void TargetInstrInfo::reassociateOps(
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MachineInstr &Root, MachineInstr &Prev,
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MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
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MachineFunction *MF = Root.getParent()->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
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// This array encodes the operand index for each parameter because the
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// operands may be commuted. Each row corresponds to a pattern value,
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// and each column specifies the index of A, B, X, Y.
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unsigned OpIdx[4][4] = {
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{ 1, 1, 2, 2 },
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{ 1, 2, 2, 1 },
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{ 2, 1, 1, 2 },
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{ 2, 2, 1, 1 }
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};
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MachineOperand &OpA = Prev.getOperand(OpIdx[Pattern][0]);
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MachineOperand &OpB = Root.getOperand(OpIdx[Pattern][1]);
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MachineOperand &OpX = Prev.getOperand(OpIdx[Pattern][2]);
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MachineOperand &OpY = Root.getOperand(OpIdx[Pattern][3]);
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MachineOperand &OpC = Root.getOperand(0);
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unsigned RegA = OpA.getReg();
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unsigned RegB = OpB.getReg();
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unsigned RegX = OpX.getReg();
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unsigned RegY = OpY.getReg();
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unsigned RegC = OpC.getReg();
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if (TargetRegisterInfo::isVirtualRegister(RegA))
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MRI.constrainRegClass(RegA, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegB))
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MRI.constrainRegClass(RegB, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegX))
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MRI.constrainRegClass(RegX, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegY))
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MRI.constrainRegClass(RegY, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegC))
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MRI.constrainRegClass(RegC, RC);
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// Create a new virtual register for the result of (X op Y) instead of
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// recycling RegB because the MachineCombiner's computation of the critical
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// path requires a new register definition rather than an existing one.
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unsigned NewVR = MRI.createVirtualRegister(RC);
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InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
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unsigned Opcode = Root.getOpcode();
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bool KillA = OpA.isKill();
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bool KillX = OpX.isKill();
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bool KillY = OpY.isKill();
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// Create new instructions for insertion.
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MachineInstrBuilder MIB1 =
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BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
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.addReg(RegX, getKillRegState(KillX))
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.addReg(RegY, getKillRegState(KillY));
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MachineInstrBuilder MIB2 =
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BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
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.addReg(RegA, getKillRegState(KillA))
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.addReg(NewVR, getKillRegState(true));
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setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
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// Record new instructions for insertion and old instructions for deletion.
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InsInstrs.push_back(MIB1);
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InsInstrs.push_back(MIB2);
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DelInstrs.push_back(&Prev);
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DelInstrs.push_back(&Root);
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}
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void TargetInstrInfo::genAlternativeCodeSequence(
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MachineInstr &Root, MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
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MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
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// Select the previous instruction in the sequence based on the input pattern.
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MachineInstr *Prev = nullptr;
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switch (Pattern) {
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case MachineCombinerPattern::MC_REASSOC_AX_BY:
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case MachineCombinerPattern::MC_REASSOC_XA_BY:
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Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
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break;
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case MachineCombinerPattern::MC_REASSOC_AX_YB:
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case MachineCombinerPattern::MC_REASSOC_XA_YB:
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Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
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break;
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default:
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break;
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}
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assert(Prev && "Unknown pattern for machine combiner");
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reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
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return;
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}
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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@ -12,7 +12,6 @@
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//===----------------------------------------------------------------------===//
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#include "AArch64InstrInfo.h"
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#include "AArch64MachineCombinerPattern.h"
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#include "AArch64Subtarget.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -1,42 +0,0 @@
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//===- AArch64MachineCombinerPattern.h -===//
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//===- AArch64 instruction pattern supported by combiner -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines instruction pattern supported by combiner
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINECOMBINERPATTERN_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINECOMBINERPATTERN_H
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namespace llvm {
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/// Enumeration of instruction pattern supported by machine combiner
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///
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///
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namespace MachineCombinerPattern {
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enum MC_PATTERN : int {
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MC_NONE = 0,
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MC_MULADDW_OP1 = 1,
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MC_MULADDW_OP2 = 2,
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MC_MULSUBW_OP1 = 3,
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MC_MULSUBW_OP2 = 4,
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MC_MULADDWI_OP1 = 5,
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MC_MULSUBWI_OP1 = 6,
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MC_MULADDX_OP1 = 7,
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MC_MULADDX_OP2 = 8,
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MC_MULSUBX_OP1 = 9,
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MC_MULSUBX_OP2 = 10,
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MC_MULADDXI_OP1 = 11,
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MC_MULSUBXI_OP1 = 12
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};
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} // end namespace MachineCombinerPattern
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} // end namespace llvm
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#endif
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@ -189,73 +189,13 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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return Latency;
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}
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static bool hasVirtualRegDefsInBasicBlock(const MachineInstr &Inst,
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const MachineBasicBlock *MBB) {
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const MachineOperand &Op1 = Inst.getOperand(1);
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const MachineOperand &Op2 = Inst.getOperand(2);
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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// We need virtual register definitions.
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MachineInstr *MI1 = nullptr;
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MachineInstr *MI2 = nullptr;
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if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
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MI1 = MRI.getUniqueVRegDef(Op1.getReg());
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if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
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MI2 = MRI.getUniqueVRegDef(Op2.getReg());
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// And they need to be in the trace (otherwise, they won't have a depth).
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if (MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB)
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return true;
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return false;
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}
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static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
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const MachineBasicBlock *MBB = Inst.getParent();
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
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MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
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unsigned AssocOpcode = Inst.getOpcode();
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// If only one operand has the same opcode and it's the second source operand,
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// the operands must be commuted.
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Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
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if (Commuted)
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std::swap(MI1, MI2);
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// 1. The previous instruction must be the same type as Inst.
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// 2. The previous instruction must have virtual register definitions for its
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// operands in the same basic block as Inst.
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// 3. The previous instruction's result must only be used by Inst.
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if (MI1->getOpcode() == AssocOpcode &&
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hasVirtualRegDefsInBasicBlock(*MI1, MBB) &&
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MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()))
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return true;
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return false;
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}
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// This function does not list all associative and commutative operations, but
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// only those worth feeding through the machine combiner in an attempt to
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// reduce the critical path. Mostly, this means floating-point operations,
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// because they have high latencies (compared to other operations, such and
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// and/or, which are also associative and commutative, but have low latencies).
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//
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// The concept is that these operations can benefit from this kind of
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// transformation:
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//
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// A = ? op ?
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// B = A op X
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// C = B op Y
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// -->
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// A = ? op ?
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// B = X op Y
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// C = A op B
|
||||
//
|
||||
// breaking the dependency between A and B, allowing them to be executed in
|
||||
// parallel (or back-to-back in a pipeline) instead of depending on each other.
|
||||
static bool isAssociativeAndCommutative(unsigned Opcode) {
|
||||
switch (Opcode) {
|
||||
bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
|
||||
switch (Inst.getOpcode()) {
|
||||
// FP Add:
|
||||
case PPC::FADD:
|
||||
case PPC::FADDS:
|
||||
@ -288,26 +228,9 @@ static bool isAssociativeAndCommutative(unsigned Opcode) {
|
||||
}
|
||||
}
|
||||
|
||||
/// Return true if the input instruction is part of a chain of dependent ops
|
||||
/// that are suitable for reassociation, otherwise return false.
|
||||
/// If the instruction's operands must be commuted to have a previous
|
||||
/// instruction of the same type define the first source operand, Commuted will
|
||||
/// be set to true.
|
||||
static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
|
||||
// 1. The operation must be associative and commutative.
|
||||
// 2. The instruction must have virtual register definitions for its
|
||||
// operands in the same basic block.
|
||||
// 3. The instruction must have a reassociable sibling.
|
||||
if (isAssociativeAndCommutative(Inst.getOpcode()) &&
|
||||
hasVirtualRegDefsInBasicBlock(Inst, Inst.getParent()) &&
|
||||
hasReassocSibling(Inst, Commuted))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
|
||||
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
|
||||
bool PPCInstrInfo::getMachineCombinerPatterns(
|
||||
MachineInstr &Root,
|
||||
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
|
||||
// Using the machine combiner in this way is potentially expensive, so
|
||||
// restrict to when aggressive optimizations are desired.
|
||||
if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
|
||||
@ -317,135 +240,7 @@ bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
|
||||
if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
|
||||
return false;
|
||||
|
||||
// Look for this reassociation pattern:
|
||||
// B = A op X (Prev)
|
||||
// C = B op Y (Root)
|
||||
|
||||
// FIXME: We should also match FMA operations here, where we consider the
|
||||
// 'part' of the FMA, either the addition or the multiplication, paired with
|
||||
// an actual addition or multiplication.
|
||||
|
||||
bool Commute;
|
||||
if (isReassocCandidate(Root, Commute)) {
|
||||
// We found a sequence of instructions that may be suitable for a
|
||||
// reassociation of operands to increase ILP. Specify each commutation
|
||||
// possibility for the Prev instruction in the sequence and let the
|
||||
// machine combiner decide if changing the operands is worthwhile.
|
||||
if (Commute) {
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_YB);
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_YB);
|
||||
} else {
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_BY);
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_BY);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// Attempt the following reassociation to reduce critical path length:
|
||||
/// B = A op X (Prev)
|
||||
/// C = B op Y (Root)
|
||||
/// ===>
|
||||
/// B = X op Y
|
||||
/// C = A op B
|
||||
static void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
|
||||
MachineCombinerPattern::MC_PATTERN Pattern,
|
||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
|
||||
MachineFunction *MF = Root.getParent()->getParent();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
|
||||
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
||||
const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
|
||||
|
||||
// This array encodes the operand index for each parameter because the
|
||||
// operands may be commuted. Each row corresponds to a pattern value,
|
||||
// and each column specifies the index of A, B, X, Y.
|
||||
unsigned OpIdx[4][4] = {
|
||||
{ 1, 1, 2, 2 },
|
||||
{ 1, 2, 2, 1 },
|
||||
{ 2, 1, 1, 2 },
|
||||
{ 2, 2, 1, 1 }
|
||||
};
|
||||
|
||||
MachineOperand &OpA = Prev.getOperand(OpIdx[Pattern][0]);
|
||||
MachineOperand &OpB = Root.getOperand(OpIdx[Pattern][1]);
|
||||
MachineOperand &OpX = Prev.getOperand(OpIdx[Pattern][2]);
|
||||
MachineOperand &OpY = Root.getOperand(OpIdx[Pattern][3]);
|
||||
MachineOperand &OpC = Root.getOperand(0);
|
||||
|
||||
unsigned RegA = OpA.getReg();
|
||||
unsigned RegB = OpB.getReg();
|
||||
unsigned RegX = OpX.getReg();
|
||||
unsigned RegY = OpY.getReg();
|
||||
unsigned RegC = OpC.getReg();
|
||||
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegA))
|
||||
MRI.constrainRegClass(RegA, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegB))
|
||||
MRI.constrainRegClass(RegB, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegX))
|
||||
MRI.constrainRegClass(RegX, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegY))
|
||||
MRI.constrainRegClass(RegY, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegC))
|
||||
MRI.constrainRegClass(RegC, RC);
|
||||
|
||||
// Create a new virtual register for the result of (X op Y) instead of
|
||||
// recycling RegB because the MachineCombiner's computation of the critical
|
||||
// path requires a new register definition rather than an existing one.
|
||||
unsigned NewVR = MRI.createVirtualRegister(RC);
|
||||
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
|
||||
|
||||
unsigned Opcode = Root.getOpcode();
|
||||
bool KillA = OpA.isKill();
|
||||
bool KillX = OpX.isKill();
|
||||
bool KillY = OpY.isKill();
|
||||
|
||||
// Create new instructions for insertion.
|
||||
MachineInstrBuilder MIB1 =
|
||||
BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
|
||||
.addReg(RegX, getKillRegState(KillX))
|
||||
.addReg(RegY, getKillRegState(KillY));
|
||||
InsInstrs.push_back(MIB1);
|
||||
|
||||
MachineInstrBuilder MIB2 =
|
||||
BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
|
||||
.addReg(RegA, getKillRegState(KillA))
|
||||
.addReg(NewVR, getKillRegState(true));
|
||||
InsInstrs.push_back(MIB2);
|
||||
|
||||
// Record old instructions for deletion.
|
||||
DelInstrs.push_back(&Prev);
|
||||
DelInstrs.push_back(&Root);
|
||||
}
|
||||
|
||||
void PPCInstrInfo::genAlternativeCodeSequence(
|
||||
MachineInstr &Root,
|
||||
MachineCombinerPattern::MC_PATTERN Pattern,
|
||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
|
||||
MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
|
||||
|
||||
// Select the previous instruction in the sequence based on the input pattern.
|
||||
MachineInstr *Prev = nullptr;
|
||||
switch (Pattern) {
|
||||
case MachineCombinerPattern::MC_REASSOC_AX_BY:
|
||||
case MachineCombinerPattern::MC_REASSOC_XA_BY:
|
||||
Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
|
||||
break;
|
||||
case MachineCombinerPattern::MC_REASSOC_AX_YB:
|
||||
case MachineCombinerPattern::MC_REASSOC_XA_YB:
|
||||
Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
|
||||
}
|
||||
assert(Prev && "Unknown pattern for machine combiner");
|
||||
|
||||
reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
|
||||
return;
|
||||
return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
|
||||
}
|
||||
|
||||
// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
|
||||
|
||||
@ -63,19 +63,6 @@ enum PPC970_Unit {
|
||||
};
|
||||
} // end namespace PPCII
|
||||
|
||||
namespace MachineCombinerPattern {
|
||||
enum MC_PATTERN : int {
|
||||
// These are commutative variants for reassociating a computation chain
|
||||
// of the form:
|
||||
// B = A op X (Prev)
|
||||
// C = B op Y (Root)
|
||||
MC_REASSOC_AX_BY = 0,
|
||||
MC_REASSOC_AX_YB = 1,
|
||||
MC_REASSOC_XA_BY = 2,
|
||||
MC_REASSOC_XA_YB = 3,
|
||||
};
|
||||
} // end namespace MachineCombinerPattern
|
||||
|
||||
class PPCSubtarget;
|
||||
class PPCInstrInfo : public PPCGenInstrInfo {
|
||||
PPCSubtarget &Subtarget;
|
||||
@ -135,21 +122,15 @@ public:
|
||||
bool useMachineCombiner() const override {
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/// Return true when there is potentially a faster code sequence
|
||||
/// for an instruction chain ending in <Root>. All potential patterns are
|
||||
/// output in the <Pattern> array.
|
||||
bool getMachineCombinerPatterns(
|
||||
MachineInstr &Root,
|
||||
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &P) const override;
|
||||
|
||||
/// When getMachineCombinerPatterns() finds a pattern, this function generates
|
||||
/// the instructions that could replace the original code sequence.
|
||||
void genAlternativeCodeSequence(
|
||||
MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
|
||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
|
||||
|
||||
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
|
||||
|
||||
bool isCoalescableExtInstr(const MachineInstr &MI,
|
||||
unsigned &SrcReg, unsigned &DstReg,
|
||||
|
||||
@ -6328,13 +6328,10 @@ hasHighOperandLatency(const TargetSchedModel &SchedModel,
|
||||
return isHighLatencyDef(DefMI->getOpcode());
|
||||
}
|
||||
|
||||
static bool hasReassociableOperands(const MachineInstr &Inst,
|
||||
const MachineBasicBlock *MBB) {
|
||||
bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
|
||||
const MachineBasicBlock *MBB) const {
|
||||
assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
|
||||
"Reassociation needs binary operators");
|
||||
const MachineOperand &Op1 = Inst.getOperand(1);
|
||||
const MachineOperand &Op2 = Inst.getOperand(2);
|
||||
const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
||||
|
||||
// Integer binary math/logic instructions have a third source operand:
|
||||
// the EFLAGS register. That operand must be both defined here and never
|
||||
@ -6349,53 +6346,15 @@ static bool hasReassociableOperands(const MachineInstr &Inst,
|
||||
if (!Inst.getOperand(3).isDead())
|
||||
return false;
|
||||
}
|
||||
|
||||
// We need virtual register definitions for the operands that we will
|
||||
// reassociate.
|
||||
MachineInstr *MI1 = nullptr;
|
||||
MachineInstr *MI2 = nullptr;
|
||||
if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
|
||||
MI1 = MRI.getUniqueVRegDef(Op1.getReg());
|
||||
if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
|
||||
MI2 = MRI.getUniqueVRegDef(Op2.getReg());
|
||||
|
||||
// And they need to be in the trace (otherwise, they won't have a depth).
|
||||
if (MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) {
|
||||
const MachineBasicBlock *MBB = Inst.getParent();
|
||||
const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
||||
MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
|
||||
MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
|
||||
unsigned AssocOpcode = Inst.getOpcode();
|
||||
|
||||
// If only one operand has the same opcode and it's the second source operand,
|
||||
// the operands must be commuted.
|
||||
Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
|
||||
if (Commuted)
|
||||
std::swap(MI1, MI2);
|
||||
|
||||
// 1. The previous instruction must be the same type as Inst.
|
||||
// 2. The previous instruction must have virtual register definitions for its
|
||||
// operands in the same basic block as Inst.
|
||||
// 3. The previous instruction's result must only be used by Inst.
|
||||
if (MI1->getOpcode() == AssocOpcode &&
|
||||
hasReassociableOperands(*MI1, MBB) &&
|
||||
MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
|
||||
}
|
||||
|
||||
// TODO: There are many more machine instruction opcodes to match:
|
||||
// 1. Other data types (integer, vectors)
|
||||
// 2. Other math / logic operations (xor, or)
|
||||
// 3. Other forms of the same operation (intrinsics and other variants)
|
||||
static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
|
||||
bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
|
||||
switch (Inst.getOpcode()) {
|
||||
case X86::AND8rr:
|
||||
case X86::AND16rr:
|
||||
@ -6468,63 +6427,12 @@ static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
|
||||
}
|
||||
}
|
||||
|
||||
/// Return true if the input instruction is part of a chain of dependent ops
|
||||
/// that are suitable for reassociation, otherwise return false.
|
||||
/// If the instruction's operands must be commuted to have a previous
|
||||
/// instruction of the same type define the first source operand, Commuted will
|
||||
/// be set to true.
|
||||
static bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) {
|
||||
// 1. The operation must be associative and commutative.
|
||||
// 2. The instruction must have virtual register definitions for its
|
||||
// operands in the same basic block.
|
||||
// 3. The instruction must have a reassociable sibling.
|
||||
if (isAssociativeAndCommutative(Inst) &&
|
||||
hasReassociableOperands(Inst, Inst.getParent()) &&
|
||||
hasReassociableSibling(Inst, Commuted))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// FIXME: This has the potential to be expensive (compile time) while not
|
||||
// improving the code at all. Some ways to limit the overhead:
|
||||
// 1. Track successful transforms; bail out if hit rate gets too low.
|
||||
// 2. Only enable at -O3 or some other non-default optimization level.
|
||||
// 3. Pre-screen pattern candidates here: if an operand of the previous
|
||||
// instruction is known to not increase the critical path, then don't match
|
||||
// that pattern.
|
||||
bool X86InstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
|
||||
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
|
||||
// TODO: There is nothing x86-specific here except the instruction type.
|
||||
// This logic could be hoisted into the machine combiner pass itself.
|
||||
|
||||
// Look for this reassociation pattern:
|
||||
// B = A op X (Prev)
|
||||
// C = B op Y (Root)
|
||||
|
||||
bool Commute;
|
||||
if (isReassociationCandidate(Root, Commute)) {
|
||||
// We found a sequence of instructions that may be suitable for a
|
||||
// reassociation of operands to increase ILP. Specify each commutation
|
||||
// possibility for the Prev instruction in the sequence and let the
|
||||
// machine combiner decide if changing the operands is worthwhile.
|
||||
if (Commute) {
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_YB);
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_YB);
|
||||
} else {
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_BY);
|
||||
Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_BY);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// This is an architecture-specific helper function of reassociateOps.
|
||||
/// Set special operand attributes for new instructions after reassociation.
|
||||
static void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
||||
MachineInstr &NewMI1, MachineInstr &NewMI2) {
|
||||
void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
|
||||
MachineInstr &OldMI2,
|
||||
MachineInstr &NewMI1,
|
||||
MachineInstr &NewMI2) const {
|
||||
// Integer instructions define an implicit EFLAGS source register operand as
|
||||
// the third source (fourth total) operand.
|
||||
if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
|
||||
@ -6532,7 +6440,7 @@ static void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
||||
|
||||
assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
|
||||
"Unexpected instruction type for reassociation");
|
||||
|
||||
|
||||
MachineOperand &OldOp1 = OldMI1.getOperand(3);
|
||||
MachineOperand &OldOp2 = OldMI2.getOperand(3);
|
||||
MachineOperand &NewOp1 = NewMI1.getOperand(3);
|
||||
@ -6559,111 +6467,6 @@ static void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
||||
NewOp2.setIsDead();
|
||||
}
|
||||
|
||||
/// Attempt the following reassociation to reduce critical path length:
|
||||
/// B = A op X (Prev)
|
||||
/// C = B op Y (Root)
|
||||
/// ===>
|
||||
/// B = X op Y
|
||||
/// C = A op B
|
||||
static void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
|
||||
MachineCombinerPattern::MC_PATTERN Pattern,
|
||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
|
||||
MachineFunction *MF = Root.getParent()->getParent();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
|
||||
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
|
||||
const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
|
||||
|
||||
// This array encodes the operand index for each parameter because the
|
||||
// operands may be commuted. Each row corresponds to a pattern value,
|
||||
// and each column specifies the index of A, B, X, Y.
|
||||
unsigned OpIdx[4][4] = {
|
||||
{ 1, 1, 2, 2 },
|
||||
{ 1, 2, 2, 1 },
|
||||
{ 2, 1, 1, 2 },
|
||||
{ 2, 2, 1, 1 }
|
||||
};
|
||||
|
||||
MachineOperand &OpA = Prev.getOperand(OpIdx[Pattern][0]);
|
||||
MachineOperand &OpB = Root.getOperand(OpIdx[Pattern][1]);
|
||||
MachineOperand &OpX = Prev.getOperand(OpIdx[Pattern][2]);
|
||||
MachineOperand &OpY = Root.getOperand(OpIdx[Pattern][3]);
|
||||
MachineOperand &OpC = Root.getOperand(0);
|
||||
|
||||
unsigned RegA = OpA.getReg();
|
||||
unsigned RegB = OpB.getReg();
|
||||
unsigned RegX = OpX.getReg();
|
||||
unsigned RegY = OpY.getReg();
|
||||
unsigned RegC = OpC.getReg();
|
||||
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegA))
|
||||
MRI.constrainRegClass(RegA, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegB))
|
||||
MRI.constrainRegClass(RegB, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegX))
|
||||
MRI.constrainRegClass(RegX, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegY))
|
||||
MRI.constrainRegClass(RegY, RC);
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegC))
|
||||
MRI.constrainRegClass(RegC, RC);
|
||||
|
||||
// Create a new virtual register for the result of (X op Y) instead of
|
||||
// recycling RegB because the MachineCombiner's computation of the critical
|
||||
// path requires a new register definition rather than an existing one.
|
||||
unsigned NewVR = MRI.createVirtualRegister(RC);
|
||||
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
|
||||
|
||||
unsigned Opcode = Root.getOpcode();
|
||||
bool KillA = OpA.isKill();
|
||||
bool KillX = OpX.isKill();
|
||||
bool KillY = OpY.isKill();
|
||||
|
||||
// Create new instructions for insertion.
|
||||
MachineInstrBuilder MIB1 =
|
||||
BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
|
||||
.addReg(RegX, getKillRegState(KillX))
|
||||
.addReg(RegY, getKillRegState(KillY));
|
||||
MachineInstrBuilder MIB2 =
|
||||
BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
|
||||
.addReg(RegA, getKillRegState(KillA))
|
||||
.addReg(NewVR, getKillRegState(true));
|
||||
|
||||
setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
|
||||
|
||||
// Record new instructions for insertion and old instructions for deletion.
|
||||
InsInstrs.push_back(MIB1);
|
||||
InsInstrs.push_back(MIB2);
|
||||
DelInstrs.push_back(&Prev);
|
||||
DelInstrs.push_back(&Root);
|
||||
}
|
||||
|
||||
void X86InstrInfo::genAlternativeCodeSequence(
|
||||
MachineInstr &Root,
|
||||
MachineCombinerPattern::MC_PATTERN Pattern,
|
||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||
DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
|
||||
MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
|
||||
|
||||
// Select the previous instruction in the sequence based on the input pattern.
|
||||
MachineInstr *Prev = nullptr;
|
||||
switch (Pattern) {
|
||||
case MachineCombinerPattern::MC_REASSOC_AX_BY:
|
||||
case MachineCombinerPattern::MC_REASSOC_XA_BY:
|
||||
Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
|
||||
break;
|
||||
case MachineCombinerPattern::MC_REASSOC_AX_YB:
|
||||
case MachineCombinerPattern::MC_REASSOC_XA_YB:
|
||||
Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
|
||||
}
|
||||
assert(Prev && "Unknown pattern for machine combiner");
|
||||
|
||||
reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
|
||||
return;
|
||||
}
|
||||
|
||||
std::pair<unsigned, unsigned>
|
||||
X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
|
||||
return std::make_pair(TF, 0u);
|
||||
|
||||
@ -26,19 +26,6 @@ namespace llvm {
|
||||
class X86RegisterInfo;
|
||||
class X86Subtarget;
|
||||
|
||||
namespace MachineCombinerPattern {
|
||||
enum MC_PATTERN : int {
|
||||
// These are commutative variants for reassociating a computation chain
|
||||
// of the form:
|
||||
// B = A op X (Prev)
|
||||
// C = B op Y (Root)
|
||||
MC_REASSOC_AX_BY = 0,
|
||||
MC_REASSOC_AX_YB = 1,
|
||||
MC_REASSOC_XA_BY = 2,
|
||||
MC_REASSOC_XA_YB = 3,
|
||||
};
|
||||
} // end namespace MachineCombinerPattern
|
||||
|
||||
namespace X86 {
|
||||
// X86 specific condition code. These correspond to X86_*_COND in
|
||||
// X86InstrInfo.td. They must be kept in synch.
|
||||
@ -451,26 +438,19 @@ public:
|
||||
const MachineInstr *DefMI, unsigned DefIdx,
|
||||
const MachineInstr *UseMI,
|
||||
unsigned UseIdx) const override;
|
||||
|
||||
|
||||
bool useMachineCombiner() const override {
|
||||
return true;
|
||||
}
|
||||
|
||||
/// Return true when there is potentially a faster code sequence
|
||||
/// for an instruction chain ending in <Root>. All potential patterns are
|
||||
/// output in the <Pattern> array.
|
||||
bool getMachineCombinerPatterns(
|
||||
MachineInstr &Root,
|
||||
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &P) const override;
|
||||
|
||||
/// When getMachineCombinerPatterns() finds a pattern, this function generates
|
||||
/// the instructions that could replace the original code sequence.
|
||||
void genAlternativeCodeSequence(
|
||||
MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
|
||||
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
||||
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
||||
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
|
||||
|
||||
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
|
||||
|
||||
bool hasReassociableOperands(const MachineInstr &Inst,
|
||||
const MachineBasicBlock *MBB) const override;
|
||||
|
||||
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
||||
MachineInstr &NewMI1,
|
||||
MachineInstr &NewMI2) const override;
|
||||
|
||||
/// analyzeCompare - For a comparison instruction, return the source registers
|
||||
/// in SrcReg and SrcReg2 if having two register operands, and the value it
|
||||
|
||||
Loading…
Reference in New Issue
Block a user