From 434fbd854bcbd43fa9f10b643bc8c89540fc33ff Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Fri, 11 Oct 2013 18:09:19 +0000 Subject: [PATCH] Revert "Tests: Be less dependent on a specific schedule/regalloc" This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. llvm-svn: 192472 --- .../2013-04-05-Small-ByVal-Structs-PR15293.ll | 10 +++---- ...013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll | 6 ++--- test/CodeGen/ARM/load-global.ll | 10 +++---- test/CodeGen/ARM/long_shift.ll | 12 ++++----- test/CodeGen/ARM/reg_sequence.ll | 4 +-- test/CodeGen/ARM/select.ll | 10 +++---- test/CodeGen/ARM/struct_byval.ll | 6 ++--- test/CodeGen/ARM/twoaddrinstr.ll | 8 +++--- test/CodeGen/ARM/vector-DAGCombine.ll | 16 ++++++------ test/CodeGen/ARM/vstlane.ll | 26 +++++++++---------- 10 files changed, 55 insertions(+), 53 deletions(-) diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll index 76c858fc6c6..127429bc31e 100644 --- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll +++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll @@ -14,9 +14,9 @@ ;CHECK-LABEL: foo2: ;CHECK: sub sp, sp, #8 ;CHECK: push {r11, lr} -;CHECK-DAG: str [[R0:r0]], [sp, #8] -;CHECK-DAG: add [[R0]], sp, #8 -;CHECK-DAG: str r2, [sp, #12] +;CHECK: str r0, [sp, #8] +;CHECK: add r0, sp, #8 +;CHECK: str r2, [sp, #12] ;CHECK: bl fooUseParam ;CHECK: add r0, sp, #12 ;CHECK: bl fooUseParam @@ -36,8 +36,8 @@ ;CHECK-LABEL: doFoo2: ;CHECK: push {r11, lr} ;CHECK: ldr r0, -;CHECK-DAG: mov r1, #0 -;CHECK-DAG: ldr r0, [r0] +;CHECK: mov r1, #0 +;CHECK: ldr r0, [r0] ;CHECK: mov r2, r0 ;CHECK: bl foo2 ;CHECK: pop {r11, lr} diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll index 3583ced36d6..6db71fed958 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll @@ -23,9 +23,9 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP entry: ;CHECK: sub sp, #8 ;CHECK: push.w {r11, lr} - ;CHECK-DAG: add r0, sp, #16 - ;CHECK-DAG: str r2, [sp, #20] - ;CHECK-DAG: str r1, [sp, #16] + ;CHECK: add r0, sp, #16 + ;CHECK: str r2, [sp, #20] + ;CHECK: str r1, [sp, #16] ;CHECK: bl fooUseStruct call void @fooUseStruct(%st_t* %p1) ret void diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll index f800b48837f..00ca2e8b1b7 100644 --- a/test/CodeGen/ARM/load-global.ll +++ b/test/CodeGen/ARM/load-global.ll @@ -39,11 +39,11 @@ define i32 @test1() { ; PIC_V7: ldr r0, [r0] ; LINUX: test1 -; LINUX-DAG: ldr [[REG0:r0]], .LCPI0_0 -; LINUX-DAG: ldr [[REG1:r1]], .LCPI0_1 -; LINUX-DAG: add [[ADDR0:r[0-9]+]], pc, [[REG0]] -; LINUX-DAG: ldr [[V0:r[0-9]+]], {{\[}}[[REG1]], [[ADDR0]]] -; LINUX: ldr r0, {{\[}}[[V0]]] +; LINUX: ldr r0, .LCPI0_0 +; LINUX: ldr r1, .LCPI0_1 +; LINUX: add r0, pc, r0 +; LINUX: ldr r0, [r1, r0] +; LINUX: ldr r0, [r0] ; LINUX: .long G(GOT) %tmp = load i32* @G ret i32 %tmp diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 66bb3364d7c..3e986d802d8 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -24,9 +24,9 @@ define i32 @f2(i64 %x, i64 %y) { ; CHECK-LABEL: f2: ; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 -; CHECK-DAG: sub r2, r2, #32 -; CHECK-DAG: orr r0, r0, r1, lsl r3 -; CHECK: cmp r2, #0 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 +; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: asrge r0, r1, r2 %a = ashr i64 %x, %y %b = trunc i64 %a to i32 @@ -37,9 +37,9 @@ define i32 @f3(i64 %x, i64 %y) { ; CHECK-LABEL: f3: ; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 -; CHECK-DAG: sub r2, r2, #32 -; CHECK-DAG: orr r0, r0, r1, lsl r3 -; CHECK: cmp r2, #0 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: orr r0, r0, r1, lsl r3 +; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: lsrge r0, r1, r2 %a = lshr i64 %x, %y %b = trunc i64 %a to i32 diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 63b5807e2f1..25484f48485 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -75,8 +75,8 @@ entry: define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ; CHECK-LABEL: t3: ; CHECK: vld3.8 -; CHECK-DAG: vmul.i8 -; CHECK-DAG: vmov r +; CHECK: vmul.i8 +; CHECK: vmov r ; CHECK-NOT: vmov d ; CHECK: vst3.8 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2] diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll index 7bf34353274..ed006d643f8 100644 --- a/test/CodeGen/ARM/select.ll +++ b/test/CodeGen/ARM/select.ll @@ -58,8 +58,8 @@ entry: define double @f7(double %a, double %b) { ;CHECK-LABEL: f7: -;CHECK-DAG: movlt -;CHECK-DAG: movge +;CHECK: movlt +;CHECK: movge ;CHECK-VFP-LABEL: f7: ;CHECK-VFP: vmovmi %tmp = fcmp olt double %a, 1.234e+00 @@ -76,9 +76,9 @@ define double @f7(double %a, double %b) { ; block generated, odds are good that we have close to the ideal code for this: ; ; CHECK-NEON-LABEL: f8: -; CHECK-NEON-DAG: movw [[R3:r[0-9]+]], #1123 -; CHECK-NEON-DAG: adr [[R2:r[0-9]+]], LCPI7_0 -; CHECK-NEON: cmp r0, [[R3]] +; CHECK-NEON: movw [[R3:r[0-9]+]], #1123 +; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0 +; CHECK-NEON-NEXT: cmp r0, [[R3]] ; CHECK-NEON-NEXT: it eq ; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4 ; CHECK-NEON-NEXT: ldr diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll index fe9fbcc85ca..012b9948537 100644 --- a/test/CodeGen/ARM/struct_byval.ll +++ b/test/CodeGen/ARM/struct_byval.ll @@ -32,9 +32,9 @@ entry: define i32 @h() nounwind ssp { entry: ; CHECK-LABEL: h: -; CHECK-DAG: vld1.32 {[[R0:d[0-9]+]], [[R1:d[0-9]+]]} -; CHECK-DAG: sub -; CHECK-DAG: vst1.32 {[[R0]], [[R1]]} +; CHECK: vld1 +; CHECK: sub +; CHECK: vst1 ; CHECK: bne %st = alloca %struct.LargeStruct, align 16 %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st) diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll index b0d7863b3b2..2172f6b9a6c 100644 --- a/test/CodeGen/ARM/twoaddrinstr.ll +++ b/test/CodeGen/ARM/twoaddrinstr.ll @@ -5,9 +5,11 @@ define void @PR13378() nounwind { ; This was orriginally a crasher trying to schedule the instructions. ; CHECK-LABEL: PR13378: ; CHECK: vld1.32 -; CHECK: vst1.32 -; CHECK: vst1.32 -; CHECK: vst1.32 +; CHECK-NEXT: vst1.32 +; CHECK-NEXT: vst1.32 +; CHECK-NEXT: vmov.f32 +; CHECK-NEXT: vmov.f32 +; CHECK-NEXT: vst1.32 entry: %0 = load <4 x float>* undef, align 4 diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index dff30ee8be4..759da2235e4 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -205,8 +205,8 @@ entry: ; CHECK-LABEL: t5: ; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0] ; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]] -; CHECK-DAG: vld1.32 {[[REG1]][0]}, [r1] -; CHECK-DAG: vld1.32 {[[REG2]][0]}, [r2] +; CHECK: vld1.32 {[[REG1]][0]}, [r1] +; CHECK: vld1.32 {[[REG2]][0]}, [r2] ; CHECK: vmull.u8 q{{[0-9]+}}, [[REG1]], [[REG2]] define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2) { entry: @@ -230,15 +230,15 @@ entry: define <2 x i8> @test_truncate(<2 x i128> %in) { ; CHECK-LABEL: test_truncate: ; CHECK: mov [[BASE:r[0-9]+]], sp -; CHECK-DAG: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32] -; CHECK-DAG: add [[BASE2:r[0-9]+]], [[BASE]], #4 -; CHECK-DAG: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32] +; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32] +; CHECK-NEXT: add [[BASE2:r[0-9]+]], [[BASE]], #4 +; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32] ; REG2 Should map on the same Q register as REG1, i.e., REG2 = REG1 - 1, but we ; cannot express that. -; CHECK-DAG: vmov.32 [[REG2:d[0-9]+]][0], r0 -; CHECK-DAG: vmov.32 [[REG2]][1], r1 +; CHECK-NEXT: vmov.32 [[REG2:d[0-9]+]][0], r0 +; CHECK-NEXT: vmov.32 [[REG2]][1], r1 ; The Q register used here should match floor(REG1/2), but we cannot express that. -; CHECK: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}} +; CHECK-NEXT: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}} ; CHECK-NEXT: vmov r0, r1, [[RES]] entry: %res = trunc <2 x i128> %in to <2 x i8> diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 17da1f007a7..34c5c70fffa 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -3,7 +3,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1lanei8: ;Check the (default) alignment. -;CHECK: vst1.8 {{{d[0-9]+}}[3]}, [r0] +;CHECK: vst1.8 {d16[3]}, [r0] %tmp1 = load <8 x i8>* %B %tmp2 = extractelement <8 x i8> %tmp1, i32 3 store i8 %tmp2, i8* %A, align 8 @@ -13,7 +13,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store. define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1lanei8_update: -;CHECK: vst1.8 {d16[3]}, [{{r[0-9]+}}]! +;CHECK: vst1.8 {d16[3]}, [{{r[0-9]}}]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B %tmp2 = extractelement <8 x i8> %tmp1, i32 3 @@ -26,7 +26,7 @@ define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vst1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: -;CHECK: vst1.16 {{{d[0-9]+}}[2]}, [r0:16] +;CHECK: vst1.16 {d16[2]}, [r0:16] %tmp1 = load <4 x i16>* %B %tmp2 = extractelement <4 x i16> %tmp1, i32 2 store i16 %tmp2, i16* %A, align 8 @@ -36,7 +36,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vst1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vst1.32 {{{d[0-9]+}}[1]}, [r0:32] +;CHECK: vst1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B %tmp2 = extractelement <2 x i32> %tmp1, i32 1 store i32 %tmp2, i32* %A, align 8 @@ -45,7 +45,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: vst1lanef: -;CHECK: vst1.32 {{{d[0-9]+}}[1]}, [r0:32] +;CHECK: vst1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x float>* %B %tmp2 = extractelement <2 x float> %tmp1, i32 1 store float %tmp2, float* %A @@ -55,7 +55,7 @@ define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vst1laneQi8: ; // Can use scalar load. No need to use vectors. -; // CHE-CK: vst1.8 {{{d[0-9]+}}[1]}, [r0] +; // CHE-CK: vst1.8 {d17[1]}, [r0] %tmp1 = load <16 x i8>* %B %tmp2 = extractelement <16 x i8> %tmp1, i32 9 store i8 %tmp2, i8* %A, align 8 @@ -64,7 +64,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vst1laneQi16: -;CHECK: vst1.16 {{{d[0-9]+}}[1]}, [r0:16] +;CHECK: vst1.16 {d17[1]}, [r0:16] %tmp1 = load <8 x i16>* %B %tmp2 = extractelement <8 x i16> %tmp1, i32 5 store i16 %tmp2, i16* %A, align 8 @@ -74,7 +74,7 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst1laneQi32: ; // Can use scalar load. No need to use vectors. -; // CHE-CK: vst1.32 {{{d[0-9]+}}[1]}, [r0:32] +; // CHE-CK: vst1.32 {d17[1]}, [r0:32] %tmp1 = load <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 store i32 %tmp2, i32* %A, align 8 @@ -85,7 +85,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst1laneQi32_update: ; // Can use scalar load. No need to use vectors. -; // CHE-CK: vst1.32 {{{d[0-9]+}}[1]}, [{{r[0-9]+}}:32]! +; // CHE-CK: vst1.32 {d17[1]}, [r1:32]! %A = load i32** %ptr %tmp1 = load <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 @@ -98,7 +98,7 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: vst1laneQf: ; // Can use scalar load. No need to use vectors. -; // CHE-CK: vst1.32 {{{d[0-9]+}}[1]}, [r0] +; // CHE-CK: vst1.32 {d17[1]}, [r0] %tmp1 = load <4 x float>* %B %tmp2 = extractelement <4 x float> %tmp1, i32 3 store float %tmp2, float* %A @@ -127,7 +127,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { ;CHECK-LABEL: vst2lanei16_update: -;CHECK: vst2.16 {d16[1], d17[1]}, [{{r[0-9]+}}], {{r[0-9]+}} +;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2 %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B @@ -251,7 +251,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check for a post-increment updating store. define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vst3laneQi32_update: -;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [{{r[0-9]+}}]! +;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]! %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B @@ -292,7 +292,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store. define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst4lanei8_update: -;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]! +;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)