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[InstCombine] allow vector splats for add+xor with low-mask
This can be allowed with undef elements too, but that can be another step: https://alive2.llvm.org/ce/z/hnC4Z-
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@ -924,9 +924,19 @@ Instruction *InstCombinerImpl::foldAddWithConstant(BinaryOperator &Add) {
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C2->isMinSignedValue() && C2->sext(Ty->getScalarSizeInBits()) == *C)
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return CastInst::Create(Instruction::SExt, X, Ty);
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// (X ^ signmask) + C --> (X + (signmask ^ C))
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if (match(Op0, m_Xor(m_Value(X), m_APInt(C2))) && C2->isSignMask())
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return BinaryOperator::CreateAdd(X, ConstantInt::get(Ty, *C2 ^ *C));
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if (match(Op0, m_Xor(m_Value(X), m_APInt(C2)))) {
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// (X ^ signmask) + C --> (X + (signmask ^ C))
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if (C2->isSignMask())
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return BinaryOperator::CreateAdd(X, ConstantInt::get(Ty, *C2 ^ *C));
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// If X has no high-bits set above an xor mask:
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// add (xor X, LowMaskC), C --> sub (LowMaskC + C), X
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if (C2->isMask()) {
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KnownBits LHSKnown = computeKnownBits(X, 0, &Add);
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if ((*C2 | LHSKnown.Zero).isAllOnesValue())
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return BinaryOperator::CreateSub(ConstantInt::get(Ty, *C2 + *C), X);
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}
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}
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if (C->isOneValue() && Op0->hasOneUse()) {
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// add (sext i1 X), 1 --> zext (not X)
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@ -1295,15 +1305,6 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
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Value *NewShl = Builder.CreateShl(XorLHS, ShAmt, "sext");
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return BinaryOperator::CreateAShr(NewShl, ShAmt);
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}
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// If X has no high-bits above the xor mask set:
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// add (xor X, LowMaskC), C --> sub (LowMaskC + C), X
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if ((XorRHS->getValue() + 1).isPowerOf2()) {
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KnownBits LHSKnown = computeKnownBits(XorLHS, 0, &I);
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if ((XorRHS->getValue() | LHSKnown.Zero).isAllOnesValue())
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return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI),
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XorLHS);
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}
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}
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}
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@ -68,8 +68,7 @@ define i32 @xor_add_extra_use(i32 %x) {
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define <2 x i8> @xor_add_splat(<2 x i8> %x) {
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; CHECK-LABEL: @xor_add_splat(
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 24, i8 24>
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; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i8> [[AND]], <i8 63, i8 63>
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; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i8> [[XOR]], <i8 42, i8 42>
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; CHECK-NEXT: [[ADD:%.*]] = sub nuw nsw <2 x i8> <i8 105, i8 105>, [[AND]]
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; CHECK-NEXT: ret <2 x i8> [[ADD]]
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;
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%and = and <2 x i8> %x, <i8 24, i8 24>
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