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Reland "[WebAssembly] v128.load{8,16,32,64}_lane instructions"
This reverts commit 7c8385a352ba21cb388046290d93b53dc273cd9f with a typing fix to an instruction selection pattern.
This commit is contained in:
Thomas Lively
parent
885b6533d2
commit
438da14930
@ -208,6 +208,52 @@ def int_wasm_load64_zero :
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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// These intrinsics do not mark their lane index arguments as immediate because
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// that changes the corresponding SDNode from ISD::Constant to
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// ISD::TargetConstant, which would require extra complications in the ISel
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// tablegen patterns. TODO: Replace these intrinsic with normal ISel patterns
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// once the load_lane instructions are merged to the proposal.
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def int_wasm_load8_lane :
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Intrinsic<[llvm_v16i8_ty],
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[LLVMPointerType<llvm_i8_ty>, llvm_v16i8_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load16_lane :
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Intrinsic<[llvm_v8i16_ty],
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[LLVMPointerType<llvm_i16_ty>, llvm_v8i16_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load32_lane :
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Intrinsic<[llvm_v4i32_ty],
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[LLVMPointerType<llvm_i32_ty>, llvm_v4i32_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load64_lane :
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Intrinsic<[llvm_v2i64_ty],
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[LLVMPointerType<llvm_i64_ty>, llvm_v2i64_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store8_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i8_ty>, llvm_v16i8_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store16_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i16_ty>, llvm_v8i16_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store32_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i32_ty>, llvm_v4i32_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store64_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i64_ty>, llvm_v2i64_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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//===----------------------------------------------------------------------===//
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// Thread-local storage intrinsics
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//===----------------------------------------------------------------------===//
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@ -421,6 +421,12 @@ public:
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return error("Expected integer constant");
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parseSingleInteger(false, Operands);
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} else {
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// v128.{load,store}{8,16,32,64}_lane has both a memarg and a lane
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// index. We need to avoid parsing an extra alignment operand for the
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// lane index.
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auto IsLoadStoreLane = InstName.find("_lane") != StringRef::npos;
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if (IsLoadStoreLane && Operands.size() == 4)
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return false;
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// Alignment not specified (or atomics, must use default alignment).
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// We can't just call WebAssembly::GetDefaultP2Align since we don't have
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// an opcode until after the assembly matcher, so set a default to fix
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@ -177,7 +177,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
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WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
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WASM_LOAD_STORE(LOAD_SPLAT_v8x16)
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return 0;
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WASM_LOAD_STORE(LOAD_LANE_v16i8)
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WASM_LOAD_STORE(STORE_LANE_v16i8)
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return 0;
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WASM_LOAD_STORE(LOAD16_S_I32)
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WASM_LOAD_STORE(LOAD16_U_I32)
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WASM_LOAD_STORE(LOAD16_S_I64)
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@ -203,7 +205,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
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WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
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WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
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WASM_LOAD_STORE(LOAD_SPLAT_v16x8)
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return 1;
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WASM_LOAD_STORE(LOAD_LANE_v8i16)
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WASM_LOAD_STORE(STORE_LANE_v8i16)
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return 1;
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WASM_LOAD_STORE(LOAD_I32)
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WASM_LOAD_STORE(LOAD_F32)
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WASM_LOAD_STORE(STORE_I32)
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@ -233,7 +237,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
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WASM_LOAD_STORE(ATOMIC_WAIT_I32)
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WASM_LOAD_STORE(LOAD_SPLAT_v32x4)
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WASM_LOAD_STORE(LOAD_ZERO_v4i32)
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return 2;
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WASM_LOAD_STORE(LOAD_LANE_v4i32)
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WASM_LOAD_STORE(STORE_LANE_v4i32)
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return 2;
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WASM_LOAD_STORE(LOAD_I64)
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WASM_LOAD_STORE(LOAD_F64)
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WASM_LOAD_STORE(STORE_I64)
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@ -256,7 +262,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
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WASM_LOAD_STORE(LOAD_EXTEND_S_v2i64)
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WASM_LOAD_STORE(LOAD_EXTEND_U_v2i64)
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WASM_LOAD_STORE(LOAD_ZERO_v2i64)
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return 3;
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WASM_LOAD_STORE(LOAD_LANE_v2i64)
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WASM_LOAD_STORE(STORE_LANE_v2i64)
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return 3;
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WASM_LOAD_STORE(LOAD_V128)
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WASM_LOAD_STORE(STORE_V128)
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return 4;
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@ -685,6 +685,56 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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Info.align = Info.memVT == MVT::i32 ? Align(4) : Align(8);
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Info.flags = MachineMemOperand::MOLoad;
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return true;
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case Intrinsic::wasm_load8_lane:
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case Intrinsic::wasm_load16_lane:
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case Intrinsic::wasm_load32_lane:
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case Intrinsic::wasm_load64_lane:
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case Intrinsic::wasm_store8_lane:
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case Intrinsic::wasm_store16_lane:
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case Intrinsic::wasm_store32_lane:
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case Intrinsic::wasm_store64_lane: {
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MVT MemVT;
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Align MemAlign;
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switch (Intrinsic) {
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case Intrinsic::wasm_load8_lane:
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case Intrinsic::wasm_store8_lane:
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MemVT = MVT::i8;
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MemAlign = Align(1);
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break;
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case Intrinsic::wasm_load16_lane:
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case Intrinsic::wasm_store16_lane:
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MemVT = MVT::i16;
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MemAlign = Align(2);
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break;
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case Intrinsic::wasm_load32_lane:
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case Intrinsic::wasm_store32_lane:
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MemVT = MVT::i32;
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MemAlign = Align(4);
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break;
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case Intrinsic::wasm_load64_lane:
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case Intrinsic::wasm_store64_lane:
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MemVT = MVT::i64;
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MemAlign = Align(8);
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break;
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default:
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llvm_unreachable("unexpected intrinsic");
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}
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if (Intrinsic == Intrinsic::wasm_load8_lane ||
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Intrinsic == Intrinsic::wasm_load16_lane ||
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Intrinsic == Intrinsic::wasm_load32_lane ||
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Intrinsic == Intrinsic::wasm_load64_lane) {
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.flags = MachineMemOperand::MOLoad;
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} else {
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Info.opc = ISD::INTRINSIC_VOID;
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Info.flags = MachineMemOperand::MOStore;
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}
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Info.ptrVal = I.getArgOperand(0);
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Info.memVT = MemVT;
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Info.offset = 0;
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Info.align = MemAlign;
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return true;
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}
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default:
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return false;
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}
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@ -53,7 +53,7 @@ defm LOAD_V128_A64 :
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"v128.load\t$off$p2align", 0>;
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}
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// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
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// Def load patterns from WebAssemblyInstrMemory.td for vector types
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foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
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defm : LoadPatNoOffset<vec_t, load, "LOAD_V128">;
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defm : LoadPatImmOff<vec_t, load, regPlusImm, "LOAD_V128">;
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@ -201,6 +201,51 @@ defm : LoadPatOffsetOnly<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">;
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defm : LoadPatGlobalAddrOffOnly<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">;
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defm : LoadPatGlobalAddrOffOnly<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">;
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// Load lane
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multiclass SIMDLoadLane<ValueType vec_t, string name, bits<32> simdop> {
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let mayLoad = 1, UseNamedOperandTable = 1 in {
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defm LOAD_LANE_#vec_t#_A32 :
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SIMD_I<(outs V128:$dst),
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(ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx,
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I32:$addr, V128:$vec),
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(outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx),
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[], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
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name#"\t$off$p2align, $idx", simdop>;
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defm LOAD_LANE_#vec_t#_A64 :
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SIMD_I<(outs V128:$dst),
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(ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx,
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I64:$addr, V128:$vec),
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(outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx),
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[], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
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name#"\t$off$p2align, $idx", simdop>;
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} // mayLoad = 1, UseNamedOperandTable = 1
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}
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// TODO: Also support v4f32 and v2f64 once the instructions are merged
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// to the proposal
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defm "" : SIMDLoadLane<v16i8, "v128.load8_lane", 88>;
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defm "" : SIMDLoadLane<v8i16, "v128.load16_lane", 89>;
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defm "" : SIMDLoadLane<v4i32, "v128.load32_lane", 90>;
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defm "" : SIMDLoadLane<v2i64, "v128.load64_lane", 91>;
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// Select loads with no constant offset.
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multiclass LoadLanePatNoOffset<ValueType ty, PatFrag kind, ImmLeaf lane_imm_t> {
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def : Pat<(ty (kind (i32 I32:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx))),
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(!cast<NI>("LOAD_LANE_"#ty#"_A32") 0, 0, imm:$idx, I32:$addr, V128:$vec)>,
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Requires<[HasAddr32]>;
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def : Pat<(ty (kind (i64 I64:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx))),
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(!cast<NI>("LOAD_LANE_"#ty#"_A64") 0, 0, imm:$idx, I64:$addr, V128:$vec)>,
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Requires<[HasAddr64]>;
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}
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defm : LoadLanePatNoOffset<v16i8, int_wasm_load8_lane, LaneIdx16>;
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defm : LoadLanePatNoOffset<v8i16, int_wasm_load16_lane, LaneIdx8>;
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defm : LoadLanePatNoOffset<v4i32, int_wasm_load32_lane, LaneIdx4>;
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defm : LoadLanePatNoOffset<v2i64, int_wasm_load64_lane, LaneIdx2>;
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// TODO: Also support the other load patterns for load_lane once the instructions
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// are merged to the proposal.
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// Store: v128.store
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let mayStore = 1, UseNamedOperandTable = 1 in {
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defm STORE_V128_A32 :
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@ -214,8 +259,9 @@ defm STORE_V128_A64 :
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"v128.store\t${off}(${addr})$p2align, $vec",
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"v128.store\t$off$p2align", 11>;
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}
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// Def store patterns from WebAssemblyInstrMemory.td for vector types
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foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
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// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
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defm : StorePatNoOffset<vec_t, store, "STORE_V128">;
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defm : StorePatImmOff<vec_t, store, regPlusImm, "STORE_V128">;
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defm : StorePatImmOff<vec_t, store, or_is_add, "STORE_V128">;
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@ -223,6 +269,53 @@ defm : StorePatOffsetOnly<vec_t, store, "STORE_V128">;
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defm : StorePatGlobalAddrOffOnly<vec_t, store, "STORE_V128">;
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}
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// Store lane
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multiclass SIMDStoreLane<ValueType vec_t, string name, bits<32> simdop> {
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let mayStore = 1, UseNamedOperandTable = 1 in {
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defm STORE_LANE_#vec_t#_A32 :
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SIMD_I<(outs),
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(ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx,
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I32:$addr, V128:$vec),
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(outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx),
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[], name#"\t${off}(${addr})$p2align, $vec, $idx",
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name#"\t$off$p2align, $idx", simdop>;
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defm STORE_LANE_#vec_t#_A64 :
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SIMD_I<(outs V128:$dst),
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(ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx,
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I64:$addr, V128:$vec),
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(outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx),
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[], name#"\t${off}(${addr})$p2align, $vec, $idx",
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name#"\t$off$p2align, $idx", simdop>;
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} // mayStore = 1, UseNamedOperandTable = 1
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}
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// TODO: Also support v4f32 and v2f64 once the instructions are merged
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// to the proposal
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defm "" : SIMDStoreLane<v16i8, "v128.store8_lane", 92>;
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defm "" : SIMDStoreLane<v8i16, "v128.store16_lane", 93>;
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defm "" : SIMDStoreLane<v4i32, "v128.store32_lane", 94>;
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defm "" : SIMDStoreLane<v2i64, "v128.store64_lane", 95>;
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// Select stores with no constant offset.
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multiclass StoreLanePatNoOffset<ValueType ty, PatFrag kind, ImmLeaf lane_imm_t> {
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def : Pat<(kind (i32 I32:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx)),
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(!cast<NI>("STORE_LANE_"#ty#"_A32")
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0, 0, imm:$idx, I32:$addr, ty:$vec)>,
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Requires<[HasAddr32]>;
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def : Pat<(kind (i64 I64:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx)),
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(!cast<NI>("STORE_LANE_"#ty#"_A64")
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0, 0, imm:$idx, I64:$addr, ty:$vec)>,
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Requires<[HasAddr64]>;
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}
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defm : StoreLanePatNoOffset<v16i8, int_wasm_store8_lane, LaneIdx16>;
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defm : StoreLanePatNoOffset<v8i16, int_wasm_store16_lane, LaneIdx8>;
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defm : StoreLanePatNoOffset<v4i32, int_wasm_store32_lane, LaneIdx4>;
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defm : StoreLanePatNoOffset<v2i64, int_wasm_store64_lane, LaneIdx2>;
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// TODO: Also support the other store patterns for store_lane once the
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// instructions are merged to the proposal.
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//===----------------------------------------------------------------------===//
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// Constructing SIMD values
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//===----------------------------------------------------------------------===//
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968
test/CodeGen/WebAssembly/simd-load-lane-offset.ll
Normal file
968
test/CodeGen/WebAssembly/simd-load-lane-offset.ll
Normal file
@ -0,0 +1,968 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
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; Test SIMD v128.load{8,16,32,64}_lane instructions.
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; TODO: Use the offset field by supporting more patterns. Right now only the
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; equivalents of LoadPatNoOffset/StorePatNoOffset are supported.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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declare <16 x i8> @llvm.wasm.load8.lane(i8*, <16 x i8>, i32)
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declare <8 x i16> @llvm.wasm.load16.lane(i16*, <8 x i16>, i32)
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declare <4 x i32> @llvm.wasm.load32.lane(i32*, <4 x i32>, i32)
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declare <2 x i64> @llvm.wasm.load64.lane(i64*, <2 x i64>, i32)
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declare void @llvm.wasm.store8.lane(i8*, <16 x i8>, i32)
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declare void @llvm.wasm.store16.lane(i16*, <8 x i16>, i32)
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declare void @llvm.wasm.store32.lane(i32*, <4 x i32>, i32)
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declare void @llvm.wasm.store64.lane(i64*, <2 x i64>, i32)
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;===----------------------------------------------------------------------------
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; v128.load8_lane / v128.store8_lane
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;===----------------------------------------------------------------------------
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define <16 x i8> @load_lane_i8_no_offset(i8* %p, <16 x i8> %v) {
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; CHECK-LABEL: load_lane_i8_no_offset:
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; CHECK: .functype load_lane_i8_no_offset (i32, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 1
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; CHECK-NEXT: v128.load8_lane 0, 0
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; CHECK-NEXT: # fallthrough-return
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%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %p, <16 x i8> %v, i32 0)
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ret <16 x i8> %t
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}
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define <16 x i8> @load_lane_i8_with_folded_offset(i8* %p, <16 x i8> %v) {
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; CHECK-LABEL: load_lane_i8_with_folded_offset:
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; CHECK: .functype load_lane_i8_with_folded_offset (i32, v128) -> (v128)
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i8* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i8*
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
define <16 x i8> @load_lane_i8_with_folded_gep_offset(i8* %p, <16 x i8> %v) {
|
||||
; CHECK-LABEL: load_lane_i8_with_folded_gep_offset:
|
||||
; CHECK: .functype load_lane_i8_with_folded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 6
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i8, i8* %p, i32 6
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
define <16 x i8> @load_lane_i8_with_unfolded_gep_negative_offset(i8* %p, <16 x i8> %v) {
|
||||
; CHECK-LABEL: load_lane_i8_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype load_lane_i8_with_unfolded_gep_negative_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const -6
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i8, i8* %p, i32 -6
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
define <16 x i8> @load_lane_i8_with_unfolded_offset(i8* %p, <16 x i8> %v) {
|
||||
; CHECK-LABEL: load_lane_i8_with_unfolded_offset:
|
||||
; CHECK: .functype load_lane_i8_with_unfolded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i8* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i8*
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
define <16 x i8> @load_lane_i8_with_unfolded_gep_offset(i8* %p, <16 x i8> %v) {
|
||||
; CHECK-LABEL: load_lane_i8_with_unfolded_gep_offset:
|
||||
; CHECK: .functype load_lane_i8_with_unfolded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 6
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i8, i8* %p, i32 6
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
define <16 x i8> @load_lane_i8_from_numeric_address(<16 x i8> %v) {
|
||||
; CHECK-LABEL: load_lane_i8_from_numeric_address:
|
||||
; CHECK: .functype load_lane_i8_from_numeric_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i8*
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
@gv_i8 = global i8 0
|
||||
define <16 x i8> @load_lane_i8_from_global_address(<16 x i8> %v) {
|
||||
; CHECK-LABEL: load_lane_i8_from_global_address:
|
||||
; CHECK: .functype load_lane_i8_from_global_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i8
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <16 x i8> @llvm.wasm.load8.lane(i8* @gv_i8, <16 x i8> %v, i32 0)
|
||||
ret <16 x i8> %t
|
||||
}
|
||||
|
||||
define void @store_lane_i8_no_offset(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_no_offset:
|
||||
; CHECK: .functype store_lane_i8_no_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store8.lane(i8* %p, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_with_folded_offset(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_with_folded_offset:
|
||||
; CHECK: .functype store_lane_i8_with_folded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i8* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i8*
|
||||
tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_with_folded_gep_offset(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_with_folded_gep_offset:
|
||||
; CHECK: .functype store_lane_i8_with_folded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 6
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i8, i8* %p, i32 6
|
||||
tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_with_unfolded_gep_negative_offset(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype store_lane_i8_with_unfolded_gep_negative_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const -6
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i8, i8* %p, i32 -6
|
||||
tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_with_unfolded_offset(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_with_unfolded_offset:
|
||||
; CHECK: .functype store_lane_i8_with_unfolded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i8* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i8*
|
||||
tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_with_unfolded_gep_offset(<16 x i8> %v, i8* %p) {
|
||||
; CHECK-LABEL: store_lane_i8_with_unfolded_gep_offset:
|
||||
; CHECK: .functype store_lane_i8_with_unfolded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 6
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i8, i8* %p, i32 6
|
||||
tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_to_numeric_address(<16 x i8> %v) {
|
||||
; CHECK-LABEL: store_lane_i8_to_numeric_address:
|
||||
; CHECK: .functype store_lane_i8_to_numeric_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i8*
|
||||
tail call void @llvm.wasm.store8.lane(i8* %s, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i8_from_global_address(<16 x i8> %v) {
|
||||
; CHECK-LABEL: store_lane_i8_from_global_address:
|
||||
; CHECK: .functype store_lane_i8_from_global_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i8
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store8_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store8.lane(i8* @gv_i8, <16 x i8> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;===----------------------------------------------------------------------------
|
||||
; v128.load16_lane / v128.store16_lane
|
||||
;===----------------------------------------------------------------------------
|
||||
|
||||
define <8 x i16> @load_lane_i16_no_offset(i16* %p, <8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_no_offset:
|
||||
; CHECK: .functype load_lane_i16_no_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %p, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define <8 x i16> @load_lane_i16_with_folded_offset(i16* %p, <8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_with_folded_offset:
|
||||
; CHECK: .functype load_lane_i16_with_folded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i16* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i16*
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define <8 x i16> @load_lane_i16_with_folded_gep_offset(i16* %p, <8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_with_folded_gep_offset:
|
||||
; CHECK: .functype load_lane_i16_with_folded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 12
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i16, i16* %p, i32 6
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define <8 x i16> @load_lane_i16_with_unfolded_gep_negative_offset(i16* %p, <8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype load_lane_i16_with_unfolded_gep_negative_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const -12
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i16, i16* %p, i32 -6
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define <8 x i16> @load_lane_i16_with_unfolded_offset(i16* %p, <8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_with_unfolded_offset:
|
||||
; CHECK: .functype load_lane_i16_with_unfolded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i16* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i16*
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define <8 x i16> @load_lane_i16_with_unfolded_gep_offset(i16* %p, <8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_with_unfolded_gep_offset:
|
||||
; CHECK: .functype load_lane_i16_with_unfolded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 12
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i16, i16* %p, i32 6
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define <8 x i16> @load_lane_i16_from_numeric_address(<8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_from_numeric_address:
|
||||
; CHECK: .functype load_lane_i16_from_numeric_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i16*
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
@gv_i16 = global i16 0
|
||||
define <8 x i16> @load_lane_i16_from_global_address(<8 x i16> %v) {
|
||||
; CHECK-LABEL: load_lane_i16_from_global_address:
|
||||
; CHECK: .functype load_lane_i16_from_global_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i16
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <8 x i16> @llvm.wasm.load16.lane(i16* @gv_i16, <8 x i16> %v, i32 0)
|
||||
ret <8 x i16> %t
|
||||
}
|
||||
|
||||
define void @store_lane_i16_no_offset(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_no_offset:
|
||||
; CHECK: .functype store_lane_i16_no_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store16.lane(i16* %p, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_with_folded_offset(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_with_folded_offset:
|
||||
; CHECK: .functype store_lane_i16_with_folded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i16* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i16*
|
||||
tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_with_folded_gep_offset(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_with_folded_gep_offset:
|
||||
; CHECK: .functype store_lane_i16_with_folded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 12
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i16, i16* %p, i32 6
|
||||
tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_with_unfolded_gep_negative_offset(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype store_lane_i16_with_unfolded_gep_negative_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const -12
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i16, i16* %p, i32 -6
|
||||
tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_with_unfolded_offset(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_with_unfolded_offset:
|
||||
; CHECK: .functype store_lane_i16_with_unfolded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i16* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i16*
|
||||
tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_with_unfolded_gep_offset(<8 x i16> %v, i16* %p) {
|
||||
; CHECK-LABEL: store_lane_i16_with_unfolded_gep_offset:
|
||||
; CHECK: .functype store_lane_i16_with_unfolded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 12
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i16, i16* %p, i32 6
|
||||
tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_to_numeric_address(<8 x i16> %v) {
|
||||
; CHECK-LABEL: store_lane_i16_to_numeric_address:
|
||||
; CHECK: .functype store_lane_i16_to_numeric_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i16*
|
||||
tail call void @llvm.wasm.store16.lane(i16* %s, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i16_from_global_address(<8 x i16> %v) {
|
||||
; CHECK-LABEL: store_lane_i16_from_global_address:
|
||||
; CHECK: .functype store_lane_i16_from_global_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i16
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store16_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store16.lane(i16* @gv_i16, <8 x i16> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;===----------------------------------------------------------------------------
|
||||
; v128.load32_lane / v128.store32_lane
|
||||
;===----------------------------------------------------------------------------
|
||||
|
||||
define <4 x i32> @load_lane_i32_no_offset(i32* %p, <4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_no_offset:
|
||||
; CHECK: .functype load_lane_i32_no_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %p, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lane_i32_with_folded_offset(i32* %p, <4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_with_folded_offset:
|
||||
; CHECK: .functype load_lane_i32_with_folded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i32* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i32*
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lane_i32_with_folded_gep_offset(i32* %p, <4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_with_folded_gep_offset:
|
||||
; CHECK: .functype load_lane_i32_with_folded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i32, i32* %p, i32 6
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lane_i32_with_unfolded_gep_negative_offset(i32* %p, <4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype load_lane_i32_with_unfolded_gep_negative_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const -24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i32, i32* %p, i32 -6
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lane_i32_with_unfolded_offset(i32* %p, <4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_with_unfolded_offset:
|
||||
; CHECK: .functype load_lane_i32_with_unfolded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i32* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i32*
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lane_i32_with_unfolded_gep_offset(i32* %p, <4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_with_unfolded_gep_offset:
|
||||
; CHECK: .functype load_lane_i32_with_unfolded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i32, i32* %p, i32 6
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define <4 x i32> @load_lane_i32_from_numeric_address(<4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_from_numeric_address:
|
||||
; CHECK: .functype load_lane_i32_from_numeric_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i32*
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
@gv_i32 = global i32 0
|
||||
define <4 x i32> @load_lane_i32_from_global_address(<4 x i32> %v) {
|
||||
; CHECK-LABEL: load_lane_i32_from_global_address:
|
||||
; CHECK: .functype load_lane_i32_from_global_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i32
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <4 x i32> @llvm.wasm.load32.lane(i32* @gv_i32, <4 x i32> %v, i32 0)
|
||||
ret <4 x i32> %t
|
||||
}
|
||||
|
||||
define void @store_lane_i32_no_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_no_offset:
|
||||
; CHECK: .functype store_lane_i32_no_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store32.lane(i32* %p, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_with_folded_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_with_folded_offset:
|
||||
; CHECK: .functype store_lane_i32_with_folded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i32* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i32*
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_with_folded_gep_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_with_folded_gep_offset:
|
||||
; CHECK: .functype store_lane_i32_with_folded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i32, i32* %p, i32 6
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_with_unfolded_gep_negative_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype store_lane_i32_with_unfolded_gep_negative_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const -24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i32, i32* %p, i32 -6
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_with_unfolded_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_with_unfolded_offset:
|
||||
; CHECK: .functype store_lane_i32_with_unfolded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i32* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i32*
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_with_unfolded_gep_offset(<4 x i32> %v, i32* %p) {
|
||||
; CHECK-LABEL: store_lane_i32_with_unfolded_gep_offset:
|
||||
; CHECK: .functype store_lane_i32_with_unfolded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i32, i32* %p, i32 6
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_to_numeric_address(<4 x i32> %v) {
|
||||
; CHECK-LABEL: store_lane_i32_to_numeric_address:
|
||||
; CHECK: .functype store_lane_i32_to_numeric_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i32*
|
||||
tail call void @llvm.wasm.store32.lane(i32* %s, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i32_from_global_address(<4 x i32> %v) {
|
||||
; CHECK-LABEL: store_lane_i32_from_global_address:
|
||||
; CHECK: .functype store_lane_i32_from_global_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i32
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store32_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store32.lane(i32* @gv_i32, <4 x i32> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;===----------------------------------------------------------------------------
|
||||
; v128.load64_lane / v128.store64_lane
|
||||
;===----------------------------------------------------------------------------
|
||||
|
||||
define <2 x i64> @load_lane_i64_no_offset(i64* %p, <2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_no_offset:
|
||||
; CHECK: .functype load_lane_i64_no_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %p, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define <2 x i64> @load_lane_i64_with_folded_offset(i64* %p, <2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_with_folded_offset:
|
||||
; CHECK: .functype load_lane_i64_with_folded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i64* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i64*
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define <2 x i64> @load_lane_i64_with_folded_gep_offset(i64* %p, <2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_with_folded_gep_offset:
|
||||
; CHECK: .functype load_lane_i64_with_folded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i64, i64* %p, i32 6
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define <2 x i64> @load_lane_i64_with_unfolded_gep_negative_offset(i64* %p, <2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype load_lane_i64_with_unfolded_gep_negative_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const -48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i64, i64* %p, i32 -6
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define <2 x i64> @load_lane_i64_with_unfolded_offset(i64* %p, <2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_with_unfolded_offset:
|
||||
; CHECK: .functype load_lane_i64_with_unfolded_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i64* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i64*
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define <2 x i64> @load_lane_i64_with_unfolded_gep_offset(i64* %p, <2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_with_unfolded_gep_offset:
|
||||
; CHECK: .functype load_lane_i64_with_unfolded_gep_offset (i32, v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: i32.const 48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i64, i64* %p, i32 6
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define <2 x i64> @load_lane_i64_from_numeric_address(<2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_from_numeric_address:
|
||||
; CHECK: .functype load_lane_i64_from_numeric_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i64*
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
@gv_i64 = global i64 0
|
||||
define <2 x i64> @load_lane_i64_from_global_address(<2 x i64> %v) {
|
||||
; CHECK-LABEL: load_lane_i64_from_global_address:
|
||||
; CHECK: .functype load_lane_i64_from_global_address (v128) -> (v128)
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i64
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.load64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%t = tail call <2 x i64> @llvm.wasm.load64.lane(i64* @gv_i64, <2 x i64> %v, i32 0)
|
||||
ret <2 x i64> %t
|
||||
}
|
||||
|
||||
define void @store_lane_i64_no_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_no_offset:
|
||||
; CHECK: .functype store_lane_i64_no_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store64.lane(i64* %p, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_with_folded_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_with_folded_offset:
|
||||
; CHECK: .functype store_lane_i64_with_folded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i64* %p to i32
|
||||
%r = add nuw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i64*
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_with_folded_gep_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_with_folded_gep_offset:
|
||||
; CHECK: .functype store_lane_i64_with_folded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i64, i64* %p, i32 6
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_with_unfolded_gep_negative_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_with_unfolded_gep_negative_offset:
|
||||
; CHECK: .functype store_lane_i64_with_unfolded_gep_negative_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const -48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr inbounds i64, i64* %p, i32 -6
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_with_unfolded_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_with_unfolded_offset:
|
||||
; CHECK: .functype store_lane_i64_with_unfolded_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 24
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%q = ptrtoint i64* %p to i32
|
||||
%r = add nsw i32 %q, 24
|
||||
%s = inttoptr i32 %r to i64*
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_with_unfolded_gep_offset(<2 x i64> %v, i64* %p) {
|
||||
; CHECK-LABEL: store_lane_i64_with_unfolded_gep_offset:
|
||||
; CHECK: .functype store_lane_i64_with_unfolded_gep_offset (v128, i32) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: local.get 1
|
||||
; CHECK-NEXT: i32.const 48
|
||||
; CHECK-NEXT: i32.add
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = getelementptr i64, i64* %p, i32 6
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_to_numeric_address(<2 x i64> %v) {
|
||||
; CHECK-LABEL: store_lane_i64_to_numeric_address:
|
||||
; CHECK: .functype store_lane_i64_to_numeric_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const 42
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
%s = inttoptr i32 42 to i64*
|
||||
tail call void @llvm.wasm.store64.lane(i64* %s, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_lane_i64_from_global_address(<2 x i64> %v) {
|
||||
; CHECK-LABEL: store_lane_i64_from_global_address:
|
||||
; CHECK: .functype store_lane_i64_from_global_address (v128) -> ()
|
||||
; CHECK-NEXT: # %bb.0:
|
||||
; CHECK-NEXT: i32.const gv_i64
|
||||
; CHECK-NEXT: local.get 0
|
||||
; CHECK-NEXT: v128.store64_lane 0, 0
|
||||
; CHECK-NEXT: # fallthrough-return
|
||||
tail call void @llvm.wasm.store64.lane(i64* @gv_i64, <2 x i64> %v, i32 0)
|
||||
ret void
|
||||
}
|
||||
@ -280,6 +280,30 @@ main:
|
||||
# CHECK: v128.bitselect # encoding: [0xfd,0x52]
|
||||
v128.bitselect
|
||||
|
||||
# CHECK: v128.load8_lane 32, 1 # encoding: [0xfd,0x58,0x00,0x20,0x01]
|
||||
v128.load8_lane 32, 1
|
||||
|
||||
# CHECK: v128.load16_lane 32, 1 # encoding: [0xfd,0x59,0x01,0x20,0x01]
|
||||
v128.load16_lane 32, 1
|
||||
|
||||
# CHECK: v128.load32_lane 32, 1 # encoding: [0xfd,0x5a,0x02,0x20,0x01]
|
||||
v128.load32_lane 32, 1
|
||||
|
||||
# CHECK: v128.load64_lane 32, 1 # encoding: [0xfd,0x5b,0x03,0x20,0x01]
|
||||
v128.load64_lane 32, 1
|
||||
|
||||
# CHECK: v128.store8_lane 32, 1 # encoding: [0xfd,0x5c,0x00,0x20,0x01]
|
||||
v128.store8_lane 32, 1
|
||||
|
||||
# CHECK: v128.store16_lane 32, 1 # encoding: [0xfd,0x5d,0x01,0x20,0x01]
|
||||
v128.store16_lane 32, 1
|
||||
|
||||
# CHECK: v128.store32_lane 32, 1 # encoding: [0xfd,0x5e,0x02,0x20,0x01]
|
||||
v128.store32_lane 32, 1
|
||||
|
||||
# CHECK: v128.store64_lane 32, 1 # encoding: [0xfd,0x5f,0x03,0x20,0x01]
|
||||
v128.store64_lane 32, 1
|
||||
|
||||
# CHECK: i8x16.abs # encoding: [0xfd,0x60]
|
||||
i8x16.abs
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user