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On some targets (e.g. X86), shift amounts are not the same as the value

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being shifted.  Don't assume they are.

llvm-svn: 24598
This commit is contained in:
Chris Lattner 2005-12-05 02:37:26 +00:00
parent 8ef7c0297c
commit 440e97cb1f
1 changed files with 6 additions and 3 deletions
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9
lib/Target/TargetSelectionDAG.td
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@ -73,6 +73,9 @@ def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
]>;
def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
]>;
def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
]>;
@ -172,9 +175,9 @@ def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
def srl : SDNode<"ISD::SRL" , SDTIntBinOp>;
def sra : SDNode<"ISD::SRA" , SDTIntBinOp>;
def shl : SDNode<"ISD::SHL" , SDTIntBinOp>;
def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
def and : SDNode<"ISD::AND" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def or : SDNode<"ISD::OR" , SDTIntBinOp,