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[mips] Update the P5600 scheduler model not to use instruction itineraries.
This mostly brings the P5600 scheduler model to a mostly complete status. There are a number of instructions which trigger the `error:'MipsP5600Model' lacks information for` error. These are certain codegen only instructions relating to MIPS64 which can be addressed by using the correct predicates for them. That will be done in a full-up patch. Patch by Simon Dardis. Differential revision: https://reviews.llvm.org/D45245 llvm-svn: 336802
This commit is contained in:
Simon Atanasyan
parent
5f7fef33e5
commit
441bff546e
@ -14,11 +14,12 @@ def MipsP5600Model : SchedMachineModel {
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int MispredictPenalty = 8; // TODO: Estimated
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let CompleteModel = 0;
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let FullInstRWOverlapCheck = 1;
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list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
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HasMips64, HasMips64r2, HasCnMips,
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HasMips3, HasMips64r2, HasCnMips,
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InMicroMips, InMips16Mode,
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HasDSP, HasDSPR2, HasMT];
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HasDSP, HasDSPR2, HasMT, HasCRC];
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}
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let SchedModel = MipsP5600Model in {
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@ -35,9 +36,8 @@ def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
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def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>;
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// and, lui, nor, or, slti, sltiu, sub, subu, xor
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def : ItinRW<[P5600WriteALU],
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[II_AND, II_LUI, II_NOR, II_OR, II_SLTI_SLTIU, II_SUB, II_SUBU,
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II_XOR]>;
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def : InstRW<[P5600WriteALU], (instrs AND, LUi, NOR, OR, SLTi, SLTiu, SUB,
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SUBu, XOR)>;
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// AGQ Pipelines
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// =============
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@ -61,20 +61,35 @@ def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> {
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// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal,
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// jalr, jr.hb, jr
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def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR,
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II_JR_HB, II_DERET, II_ERET, II_ERETNC,
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II_SYSCALL, II_BREAK, II_SDBBP, II_SSNOP,
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II_TEQ, II_TEQI, II_TGE, II_TGEI, II_TGEIU,
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II_TGEU, II_TLT, II_TLTI, II_TLTU, II_TNE,
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II_TNEI, II_TRAP, II_TTLTIU, II_WAIT,
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II_PAUSE]>;
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def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL,
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BGEZALL, BGEZL, BGTZ, BGTZL, BLEZ, BLEZL, BLTZ,
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BLTZAL, BLTZALL, BLTZL, BNE, BNEL, BREAK,
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DERET, ERET, ERETNC, J, JR, JR_HB,
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PseudoIndirectBranch,
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PseudoIndirectHazardBranch, PseudoReturn,
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SDBBP, SSNOP, SYSCALL, TAILCALL, TAILCALLREG,
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TAILCALLREGHB, TEQ, TEQI, TGE, TGEI, TGEIU,
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TGEU, TLT, TLTI, TLTU, TNE, TNEI, TRAP,
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TTLTIU, WAIT, PAUSE)>;
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def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB]>;
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def : InstRW<[P5600WriteJumpAndLink], (instrs JAL, JALR, JALRHBPseudo,
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JALRPseudo, JALR_HB)>;
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def : InstRW<[P5600WriteJumpAndLink], (instrs JALX)> {
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let Unsupported = 1;
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}
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def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
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def : ItinRW<[P5600COP0], [II_TLBINV, II_TLBINVF, II_TLBP, II_TLBR, II_TLBWI,
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II_TLBWR, II_MFC0, II_MTC0]>;
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def : InstRW<[P5600COP0], (instrs TLBINV, TLBINVF, TLBP, TLBR, TLBWI, TLBWR,
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MFC0, MTC0)>;
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def P5600COP2 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
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def : InstRW<[P5600COP2], (instrs MFC2, MTC2)> {
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let Unsupported = 1;
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}
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// LDST Pipeline
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// -------------
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@ -104,21 +119,20 @@ def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
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}
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// l[bhw], l[bh]u, ll
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def : ItinRW<[P5600WriteLoad], [II_LB, II_LBE, II_LBU, II_LBUE, II_LH, II_LHE,
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II_LHU, II_LHUE, II_LW, II_LWE, II_LL, II_LLE,
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II_LWPC]>;
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def : InstRW<[P5600WriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, LWC2, LWC3,
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LDC2, LDC3, LBE, LBuE, LHE, LHuE, LWE, LLE,
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LWPC)>;
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// lw[lr]
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def : ItinRW<[P5600WriteLoadShifted], [II_LWL, II_LWLE, II_LWR, II_LWRE]>;
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def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
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// s[bhw], sw[lr]
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def : ItinRW<[P5600WriteStore], [II_SB, II_SBE, II_SH, II_SHE, II_SW, II_SWE,
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II_SWL, II_SWLE, II_SWR, II_SWRE, II_SC,
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II_SCE]>;
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def : InstRW<[P5600WriteStore], (instrs SB, SH, SW, SWC2, SWC3, SDC2, SDC3, SC,
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SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>;
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// pref, cache, sync, synci
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def : ItinRW<[P5600WriteCache], [II_PREF, II_PREFE, II_CACHE, II_CACHEE,
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II_SYNC, II_SYNCI]>;
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def : InstRW<[P5600WriteCache], (instrs PREF, PREFE, CACHE, CACHEE, SYNC,
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SYNCI)>;
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// LDST is also used in moves from general purpose registers to floating point
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// and MSA.
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@ -152,28 +166,31 @@ def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
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}
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// clo, clz, di, ei, mfhi, mflo
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def : ItinRW<[P5600WriteAL2], [II_CLO, II_CLZ, II_DI, II_EI, II_MFHI_MFLO]>;
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def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
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PseudoMFHI, PseudoMFLO)>;
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// ehb, rdhwr, rdpgpr, wrpgpr, wsbh
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def : ItinRW<[P5600WriteAL2ShadowMov], [II_EHB, II_RDHWR, II_WSBH]>;
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def : InstRW<[P5600WriteAL2ShadowMov], (instrs EHB, RDHWR, WSBH)>;
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// mov[nz]
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def : ItinRW<[P5600WriteAL2CondMov], [II_MOVN, II_MOVZ]>;
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def : InstRW<[P5600WriteAL2CondMov], (instrs MOVN_I_I, MOVZ_I_I)>;
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// divu?
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def : ItinRW<[P5600WriteAL2Div], [II_DIV]>;
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def : ItinRW<[P5600WriteAL2DivU], [II_DIVU]>;
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def : InstRW<[P5600WriteAL2Div], (instrs DIV, PseudoSDIV, SDIV)>;
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def : InstRW<[P5600WriteAL2DivU], (instrs DIVU, PseudoUDIV, UDIV)>;
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// mul
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def : ItinRW<[P5600WriteAL2Mul], [II_MUL]>;
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def : InstRW<[P5600WriteAL2Mul], (instrs MUL)>;
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// multu?, multu?
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def : ItinRW<[P5600WriteAL2Mult], [II_MULT, II_MULTU]>;
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def : InstRW<[P5600WriteAL2Mult], (instrs MULT, MULTu, PseudoMULT,
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PseudoMULTu)>;
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// maddu?, msubu?, mthi, mtlo
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def : ItinRW<[P5600WriteAL2MAdd],
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[II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_MTHI_MTLO]>;
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def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU,
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MTHI, MTLO, PseudoMADD, PseudoMADDU,
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PseudoMSUB, PseudoMSUBU, PseudoMTLOHI)>;
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// ext, ins
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def : ItinRW<[P5600WriteAL2BitExt], [II_EXT, II_INS]>;
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def : InstRW<[P5600WriteAL2BitExt], (instrs EXT, INS)>;
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// Either ALU or AL2 Pipelines
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// ---------------------------
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@ -191,11 +208,9 @@ def P5600WriteEitherALU : SchedWriteVariant<
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// add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
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// xori
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def : ItinRW<[P5600WriteEitherALU],
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[II_ADD, II_ADDI, II_ADDIU, II_ANDI, II_ORI, II_ROTR, II_SEB, II_SEH,
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II_SLT_SLTU, II_SLL, II_SRA, II_SRL, II_XORI, II_ADDU, II_SLLV,
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II_SRAV, II_SRLV, II_LSA]>;
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def : InstRW<[], (instrs COPY)>;
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def : InstRW<[P5600WriteEitherALU], (instrs ADD, ADDi, ADDiu, ANDi, ORi, ROTR,
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SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
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ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
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// FPU Pipelines
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// =============
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@ -298,8 +313,10 @@ def P5600WriteMoveFPULToOtherUnits : SchedWriteRes<[P5600IssueFPUL]>;
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// abs.[ds], abs.ps, bc1[tf]l?, mov[tf].[ds], mov[tf], mov.[ds], [cm][ft]c1,
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// m[ft]hc1, neg.[ds], neg.ps, nor.v, nori.b, or.v, ori.b, xor.v, xori.b,
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// sdxc1, sdc1, st.[bhwd], swc1, swxc1
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def : ItinRW<[P5600WriteFPUS], [II_ABS, II_MOVF_D, II_MOVF_S, II_MOVT_D,
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II_MOVT_S, II_MOV_D, II_MOV_S, II_NEG]>;
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def : InstRW<[P5600WriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, MOVF_D32,
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MOVF_D64, MOVF_S, MOVT_D32, MOVT_D64,
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MOVT_S, FMOV_D32, FMOV_D64, FMOV_S, FNEG_S,
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FNEG_D32, FNEG_D64)>;
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// adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd],
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// aver?_[us].[bhwd], shf.[bhw], fill[bhwd], splat?.[bhwd]
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@ -412,24 +429,31 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>;
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// add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps,
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// cvt.ps.[sw], c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, sub.[ds], sub.ps,
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// trunc.w.[ds], trunc.w.ps
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def : ItinRW<[P5600WriteFPUL],
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[II_ADD_D, II_ADD_S, II_CVT, II_C_CC_D, II_C_CC_S, II_MUL_D,
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II_MUL_S, II_SUB_D, II_SUB_S, II_TRUNC]>;
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def : InstRW<[P5600WriteFPUL],
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(instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
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FSUB_D32, FSUB_D64, FSUB_S)>;
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def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>;
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def : InstRW<[P5600WriteFPUL],
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(instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>;
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def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>;
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def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>;
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def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>;
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// div.[ds], div.ps
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def : ItinRW<[P5600WriteFPUDivS], [II_DIV_S]>;
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def : ItinRW<[P5600WriteFPUDivD], [II_DIV_D]>;
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def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>;
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def : InstRW<[P5600WriteFPUDivD], (instrs FDIV_D32, FDIV_D64)>;
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// sqrt.[ds], sqrt.ps
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def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>;
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def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
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def : InstRW<[P5600WriteFPUSqrtS], (instrs FSQRT_S)>;
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def : InstRW<[P5600WriteFPUSqrtD], (instrs FSQRT_D32, FSQRT_D64)>;
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// frcp.[wd], frsqrt.[wd]
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def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>;
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def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>;
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def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>;
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def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>;
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def : InstRW<[P5600WriteFPURsqrtD], (instrs RECIP_D32, RECIP_D64, RSQRT_D32,
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RSQRT_D64)>;
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def : InstRW<[P5600WriteFPURsqrtS], (instrs RECIP_S, RSQRT_S)>;
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// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd],
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// fsub.[wd]
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@ -461,9 +485,9 @@ def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
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// madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds],
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// Operand 0 is read on cycle 5. All other operands are read on operand 0.
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def : ItinRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB],
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[II_MADD_D, II_MADD_S, II_MSUB_D, II_MSUB_S, II_NMADD_D,
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II_NMADD_S, II_NMSUB_D, II_NMSUB_S]>;
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def : InstRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB],
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(instrs MADD_D32, MADD_D64, MADD_S, MSUB_D32, MSUB_D64, MSUB_S,
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NMADD_D32, NMADD_D64, NMADD_S, NMSUB_D32, NMSUB_D64, NMSUB_S)>;
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// madd.ps, msub.ps, nmadd.ps, nmsub.ps
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// Operand 0 and 1 are read on cycle 5. All others are read on operand 0.
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@ -516,26 +540,30 @@ def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits,
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P5600WriteLoadOtherUnitsToFPU]>;
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// ctc1, mtc1, mthc1
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def : ItinRW<[P5600WriteMoveGPRToFPU], [II_CTC1, II_MTC1, II_MTHC1]>;
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def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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MTHC1_D64, BuildPairF64,
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BuildPairF64_64)>;
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// copy.[su]_[bhwd]
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def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_U_[BHW]$")>;
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def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_S_[BHWD]$")>;
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// bc1[ft], cfc1, mfc1, mfhc1, movf, movt
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def : ItinRW<[P5600WriteMoveFPUToGPR],
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[II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
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def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1,
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MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64,
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MOVF_I, MOVT_I, ExtractElementF64,
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ExtractElementF64_64)>;
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// swc1, swxc1, st.[bhwd]
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def : ItinRW<[P5600WriteStoreFPUS], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1,
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II_SWXC1]>;
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def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDXC1, SUXC1, SWC1, SWXC1)>;
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def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>;
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// movn.[ds], movz.[ds]
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def : ItinRW<[P5600WriteStoreFPUL], [II_MOVN_D, II_MOVN_S, II_MOVZ_D, II_MOVZ_S]>;
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def : InstRW<[P5600WriteStoreFPUL], (instrs MOVN_I_D32, MOVN_I_D64, MOVN_I_S,
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MOVZ_I_D32, MOVZ_I_D64, MOVZ_I_S)>;
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// l[dw]x?c1, ld.[bhwd]
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def : ItinRW<[P5600WriteLoadFPU], [II_LDC1, II_LDXC1, II_LWC1, II_LWXC1, II_LUXC1]>;
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def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDXC1, LWC1, LWXC1, LUXC1)>;
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def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>;
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// Unsupported Instructions
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@ -557,10 +585,12 @@ def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>;
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// ceil.[lw].[ds], floor.[lw].[ds]
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// Reason behind guess: trunc.[lw].ds and the various cvt's are in FPUL
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def : ItinRW<[P5600WriteFPUL], [II_CEIL, II_FLOOR, II_ROUND]>;
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def : InstRW<[P5600WriteFPUL], (instregex "^CEIL_(L|W)_(S|D32|D64)$")>;
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def : InstRW<[P5600WriteFPUL], (instregex "^FLOOR_(L|W)_(S|D32|D64)$")>;
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def : InstRW<[P5600WriteFPUL], (instregex "^ROUND_(L|W)_(S|D32|D64)$")>;
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// rotrv
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// Reason behind guess: rotr is in the same category and the two register forms
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// generally follow the immediate forms in this category
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def : ItinRW<[P5600WriteEitherALU], [II_ROTRV]>;
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def : InstRW<[P5600WriteEitherALU], (instrs ROTRV)>;
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}
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