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[VE] Add VBRD/VMV instructions
Add VBRD/VMV vector instructions. In order to do that, also support VM512 registers and RV instruction format in MC layer. Also add regression tests for new instructions. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D89641
This commit is contained in:
Kazushi (Jam) Marukawa
parent
ddfd67dc64
commit
443ef62a38
@ -125,6 +125,9 @@ static const MCPhysReg F128Regs[32] = {
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VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
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VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
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static const MCPhysReg VM512Regs[8] = {VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3,
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VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};
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static const MCPhysReg MISCRegs[31] = {
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VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
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VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
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@ -648,6 +651,15 @@ public:
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return true;
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}
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static bool MorphToVM512Reg(VEOperand &Op) {
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unsigned Reg = Op.getReg();
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unsigned regIdx = Reg - VE::VM0;
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if (regIdx % 2 || regIdx > 15)
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return false;
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Op.Reg.RegNum = VM512Regs[regIdx / 2];
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return true;
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}
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static bool MorphToMISCReg(VEOperand &Op) {
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const auto *ConstExpr = dyn_cast<MCConstantExpr>(Op.getImm());
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if (!ConstExpr)
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@ -1462,6 +1474,10 @@ unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
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if (Op.isReg() && VEOperand::MorphToF128Reg(Op))
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return MCTargetAsmParser::Match_Success;
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break;
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case MCK_VM512:
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if (Op.isReg() && VEOperand::MorphToVM512Reg(Op))
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return MCTargetAsmParser::Match_Success;
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break;
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case MCK_MISC:
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if (Op.isImm() && VEOperand::MorphToMISCReg(Op))
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return MCTargetAsmParser::Match_Success;
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@ -237,8 +237,43 @@ class RVM<bits<8>opVal, dag outs, dag ins, string asmstr,
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//-----------------------------------------------------------------------------
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// Section 5.7 RV Type
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//
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// RV type is for vector instructions.
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//-----------------------------------------------------------------------------
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class RV<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<1> cx2 = 0;
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bits<1> cs = 0;
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bits<1> cs2 = 0;
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bits<4> m = 0;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 0;
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bits<7> sz = 0;
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bits<8> vx = 0;
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bits<8> vy = 0;
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bits<8> vz = 0;
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bits<8> vw = 0;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54} = cx2;
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let Inst{53} = cs;
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let Inst{52} = cs2;
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let Inst{51-48} = m;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-24} = vx;
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let Inst{23-16} = vy;
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let Inst{15-8} = vz;
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let Inst{7-0} = vw;
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let VE_Vector = 1;
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}
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// Pseudo instructions.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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@ -352,3 +352,84 @@ multiclass SVMm<string opcStr, bits<8>opc, RegisterClass RCM> {
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opcStr#" $sx, $vz, $sy">;
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}
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defm SVM : SVMm<"svm", 0xa7, VM>;
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// Section 8.9.24 - VBRD (Vector Broadcast)
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let vx = ?, hasSideEffects = 0, Uses = [VL] in
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multiclass VBRDbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in, string disEnc = ""> {
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let DisableEncoding = disEnc in
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def "" : RV<opc, (outs RC:$vx), dag_in,
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!strconcat(opcStr, " $vx, ", argStr)>;
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let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
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isCodeGenOnly = 1 in
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def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
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!strconcat(opcStr, " $vx, ", argStr)>;
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}
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multiclass VBRDlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in> {
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defm "" : VBRDbm<opcStr, argStr, opc, RC, dag_in>;
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let isCodeGenOnly = 1, VE_VLInUse = 1 in {
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defm l : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
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"$vl,">;
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defm L : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
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"$vl,">;
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}
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}
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multiclass VBRDmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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RegisterClass RCM, dag dag_in> {
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defm "" : VBRDlm<opcStr, argStr, opc, RC, dag_in>;
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let m = ?, VE_VLWithMask = 1 in
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defm m : VBRDlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
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}
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let VE_VLIndex = 2 in
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multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
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RegisterClass RCM> {
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defm r : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins RC:$sy)>;
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let cy = 0 in
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defm i : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins simm7:$sy)>;
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}
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let cx = 0, cx2 = 0 in
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defm VBRD : VBRDm<"vbrd", 0x8c, V64, I64, VM>;
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let cx = 0, cx2 = 1 in
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defm VBRDL : VBRDm<"vbrdl", 0x8c, V64, I32, VM>;
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let cx = 1, cx2 = 0 in
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defm VBRDU : VBRDm<"vbrdu", 0x8c, V64, F32, VM>;
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let cx = 1, cx2 = 1 in
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defm PVBRD : VBRDm<"pvbrd", 0x8c, V64, I64, VM512>;
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// Section 8.9.25 - VMV (Vector Move)
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let vx = ?, vz = ?, hasSideEffects = 0, Uses = [VL] in
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multiclass VMVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in, string disEnc = ""> {
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let DisableEncoding = disEnc in
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def "" : RV<opc, (outs RC:$vx), dag_in,
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!strconcat(opcStr, " $vx, ", argStr)>;
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let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
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isCodeGenOnly = 1 in
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def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
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!strconcat(opcStr, " $vx, ", argStr)>;
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}
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multiclass VMVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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dag dag_in> {
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defm "" : VMVbm<opcStr, argStr, opc, RC, dag_in>;
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let isCodeGenOnly = 1, VE_VLInUse = 1 in {
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defm l : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
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"$vl,">;
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defm L : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
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"$vl,">;
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}
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}
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multiclass VMVmm<string opcStr, bits<8>opc, RegisterClass RC,
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RegisterClass RCM, dag dag_in> {
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defm "" : VMVlm<opcStr, "$sy, $vz", opc, RC, dag_in>;
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let m = ?, VE_VLWithMask = 1 in
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defm m : VMVlm<opcStr, "$sy, $vz, $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
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}
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let VE_VLIndex = 3 in
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multiclass VMVm<string opcStr, bits<8>opc, RegisterClass RC,
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RegisterClass RCM> {
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defm rv : VMVmm<opcStr, opc, RC, RCM, (ins I64:$sy, RC:$vz)>;
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let cy = 0 in
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defm iv : VMVmm<opcStr, opc, RC, RCM, (ins uimm7:$sy, RC:$vz)>;
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}
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defm VMV : VMVm<"vmv", 0x9c, V64, VM>;
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52
test/MC/VE/VBRD.s
Normal file
52
test/MC/VE/VBRD.s
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@ -0,0 +1,52 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vbrd %v11, 23
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x17,0x00,0x8c]
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vbrd %v11, 23
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# CHECK-INST: vbrd %v11, %s12, %vm15
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x8c,0x0f,0x8c]
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vbrd %v11, %s12, %vm15
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# CHECK-INST: vbrd %vix, %s22
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x00,0x96,0x00,0x8c]
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vbrd %vix, %s22, %vm0
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# CHECK-INST: vbrdl %v11, 23
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x17,0x40,0x8c]
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vbrdl %v11, 23
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# CHECK-INST: vbrdl %v11, %s12, %vm15
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x8c,0x4f,0x8c]
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vbrdl %v11, %s12, %vm15
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# CHECK-INST: vbrdl %vix, %s22
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x00,0x96,0x40,0x8c]
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vbrdl %vix, %s22, %vm0
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# CHECK-INST: vbrdu %v11, 23
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x17,0x80,0x8c]
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vbrdu %v11, 23
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# CHECK-INST: vbrdu %v11, %s12, %vm15
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x8c,0x8f,0x8c]
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vbrdu %v11, %s12, %vm15
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# CHECK-INST: vbrdu %vix, %s22
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x00,0x96,0x80,0x8c]
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vbrdu %vix, %s22, %vm0
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# CHECK-INST: pvbrd %v11, 23
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x17,0xc0,0x8c]
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pvbrd %v11, 23
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# CHECK-INST: pvbrd %v11, %s12, %vm14
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x00,0x8c,0xce,0x8c]
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pvbrd %v11, %s12, %vm14
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# CHECK-INST: pvbrd %vix, %s22
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# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x00,0x96,0xc0,0x8c]
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pvbrd %vix, %s22, %vm0
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16
test/MC/VE/VMV.s
Normal file
16
test/MC/VE/VMV.s
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@ -0,0 +1,16 @@
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# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vmv %v11, 23, %v11
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# CHECK-ENCODING: encoding: [0x00,0x0b,0x00,0x0b,0x00,0x17,0x00,0x9c]
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vmv %v11, 23, %v11
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# CHECK-INST: vmv %v11, %s12, %vix, %vm15
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# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0x0b,0x00,0x8c,0x0f,0x9c]
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vmv %v11, %s12, %vix, %vm15
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# CHECK-INST: vmv %vix, 127, %v63
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# CHECK-ENCODING: encoding: [0x00,0x3f,0x00,0xff,0x00,0x7f,0x00,0x9c]
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vmv %vix, 127, %v63, %vm0
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