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[AMDGPU] Sign extend AShr when promoting (instead of zero extending)
llvm-svn: 283130
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c250a100e2
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@ -172,8 +172,8 @@ bool AMDGPUCodeGenPrepare::isI32Ty(const Type *T) const {
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}
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bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
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return I.getOpcode() == Instruction::SDiv ||
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I.getOpcode() == Instruction::SRem;
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return I.getOpcode() == Instruction::AShr ||
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I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
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}
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bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {
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@ -226,8 +226,8 @@ define i16 @lshr_exact_i16(i16 %a, i16 %b) {
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}
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; VI-LABEL: @ashr_i16(
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; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
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; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
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; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
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; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
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; VI: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]]
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; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
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; VI: ret i16 %[[R_16]]
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@ -237,8 +237,8 @@ define i16 @ashr_i16(i16 %a, i16 %b) {
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}
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; VI-LABEL: @ashr_exact_i16(
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; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
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; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
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; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
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; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
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; VI: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
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; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
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; VI: ret i16 %[[R_16]]
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@ -651,8 +651,8 @@ define <3 x i16> @lshr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) {
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}
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; VI-LABEL: @ashr_3xi16(
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; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
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; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
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; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
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; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
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; VI: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]]
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; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
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; VI: ret <3 x i16> %[[R_16]]
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@ -662,8 +662,8 @@ define <3 x i16> @ashr_3xi16(<3 x i16> %a, <3 x i16> %b) {
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}
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; VI-LABEL: @ashr_exact_3xi16(
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; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
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; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
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; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
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; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
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; VI: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]]
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; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
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; VI: ret <3 x i16> %[[R_16]]
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