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[InstCombine] Be consistent w/handling of masked intrinsics style wise [NFC]
llvm-svn: 359160
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@ -1179,8 +1179,7 @@ static APInt possiblyDemandedEltsInMask(Value *Mask) {
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// TODO, Obvious Missing Transforms:
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// * Narrow width by halfs excluding zero/undef lanes
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static Value *simplifyMaskedLoad(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder) {
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Value *InstCombiner::simplifyMaskedLoad(IntrinsicInst &II) {
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Value *LoadPtr = II.getArgOperand(0);
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unsigned Alignment = cast<ConstantInt>(II.getArgOperand(1))->getZExtValue();
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@ -1241,7 +1240,7 @@ Instruction *InstCombiner::simplifyMaskedStore(IntrinsicInst &II) {
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// * Narrow width by halfs excluding zero/undef lanes
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// * Vector splat address w/known mask -> scalar load
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// * Vector incrementing address -> vector masked load
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static Instruction *simplifyMaskedGather(IntrinsicInst &II, InstCombiner &IC) {
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Instruction *InstCombiner::simplifyMaskedGather(IntrinsicInst &II) {
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return nullptr;
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}
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@ -2018,13 +2017,13 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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case Intrinsic::masked_load:
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if (Value *SimplifiedMaskedOp = simplifyMaskedLoad(*II, Builder))
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if (Value *SimplifiedMaskedOp = simplifyMaskedLoad(*II))
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return replaceInstUsesWith(CI, SimplifiedMaskedOp);
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break;
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case Intrinsic::masked_store:
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return simplifyMaskedStore(*II);
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case Intrinsic::masked_gather:
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return simplifyMaskedGather(*II, *this);
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return simplifyMaskedGather(*II);
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case Intrinsic::masked_scatter:
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return simplifyMaskedScatter(*II);
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case Intrinsic::launder_invariant_group:
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@ -478,7 +478,9 @@ private:
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Instruction *transformCallThroughTrampoline(CallBase &Call,
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IntrinsicInst &Tramp);
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Value *simplifyMaskedLoad(IntrinsicInst &II);
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Instruction *simplifyMaskedStore(IntrinsicInst &II);
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Instruction *simplifyMaskedGather(IntrinsicInst &II);
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Instruction *simplifyMaskedScatter(IntrinsicInst &II);
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/// Transform (zext icmp) to bitwise / integer operations in order to
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