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Fix a couple bugs in the const div stuff where we'd generate MULHS/MULHU

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for types that aren't legal, and fail a divisor is less than zero
comparison, which would cause us to drop a subtract.

llvm-svn: 23846
This commit is contained in:
Nate Begeman 2005-10-20 17:45:03 +00:00
parent 1f9a14683a
commit 44712926a0
1 changed files with 4 additions and 3 deletions
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7
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -790,7 +790,8 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
// detect that too.
if (N1C && !isPowerOf2_64(N1C->getSignExtended()) &&
(N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isIntDivExpensive()) {
TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isTypeLegal(VT) &&
TLI.isIntDivExpensive()) {
return BuildSDIV(N);
}
return SDOperand();
@ -814,7 +815,7 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) {
TLI.getShiftAmountTy()));
// fold (udiv x, c) -> alternate
if (N1C && N1C->getValue() && TLI.isOperationLegal(ISD::MULHU, VT) &&
TLI.isIntDivExpensive())
TLI.isTypeLegal(VT) && TLI.isIntDivExpensive())
return BuildUDIV(N);
return SDOperand();
}
@ -2555,7 +2556,7 @@ SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
assert((VT == MVT::i32 || VT == MVT::i64) &&
"BuildSDIV only operates on i32 or i64!");
int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
// Multiply the numerator (operand 0) by the magic value