1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00

Use movaps / movapd to spill / restore V4F4 / V2F8 registers.

llvm-svn: 26240
This commit is contained in:
Evan Cheng 2006-02-16 21:20:26 +00:00
parent 70d21494ed
commit 447c171afd

View File

@ -57,10 +57,14 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
Opc = X86::MOV16mr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpST64m;
} else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
} else if (RC == &X86::FR32RegClass) {
Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
} else if (RC == &X86::V4F4RegClass) {
Opc = X86::MOVAPSmr;
} else if (RC == &X86::V2F8RegClass) {
Opc = X86::MOVAPDmr;
} else {
assert(0 && "Unknown regclass");
abort();
@ -81,10 +85,14 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Opc = X86::MOV16rm;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpLD64m;
} else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
} else if (RC == &X86::FR32RegClass) {
Opc = X86::MOVSSrm;
} else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDrm;
} else if (RC == &X86::V4F4RegClass) {
Opc = X86::MOVAPSrm;
} else if (RC == &X86::V2F8RegClass) {
Opc = X86::MOVAPDrm;
} else {
assert(0 && "Unknown regclass");
abort();