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[ARM][MVE] Fix copy-paste error in VQSHL instruction ids.

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Summary:
The immediate forms of the MVE VQSHL instruction have MC names like
`MVE_VSLIimms8` and `MVE_VSLIimmu32`. Those names are confusing,
because VSLI is a completely different shift instruction with no
semantic relation to VQSHL. But it just happens to be defined
immediately before VQSHL in `ARMInstrMVE.td`, so this looks like a
copy-paste error. Renamed the ids to match the instruction name.

Reviewers: ostannard, dmgreen, MarkMurrayARM, miyuki

Reviewed By: miyuki

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71114
This commit is contained in:
Simon Tatham 2019-12-06 15:23:07 +00:00
parent 6a285a1aba
commit 449029437c
2 changed files with 12 additions and 12 deletions
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12
lib/Target/ARM/ARMInstrMVE.td
View File

@ -2529,32 +2529,32 @@ class MVE_VQSHL_imm<string suffix, dag imm>
let Inst{10-8} = 0b111; let Inst{10-8} = 0b111;
} }
def MVE_VSLIimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> { def MVE_VQSHLimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
let Inst{28} = 0b0; let Inst{28} = 0b0;
let Inst{21-19} = 0b001; let Inst{21-19} = 0b001;
} }
def MVE_VSLIimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> { def MVE_VQSHLimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
let Inst{28} = 0b1; let Inst{28} = 0b1;
let Inst{21-19} = 0b001; let Inst{21-19} = 0b001;
} }
def MVE_VSLIimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> { def MVE_VQSHLimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
let Inst{28} = 0b0; let Inst{28} = 0b0;
let Inst{21-20} = 0b01; let Inst{21-20} = 0b01;
} }
def MVE_VSLIimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> { def MVE_VQSHLimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
let Inst{28} = 0b1; let Inst{28} = 0b1;
let Inst{21-20} = 0b01; let Inst{21-20} = 0b01;
} }
def MVE_VSLIimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> { def MVE_VQSHLimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
let Inst{28} = 0b0; let Inst{28} = 0b0;
let Inst{21} = 0b1; let Inst{21} = 0b1;
} }
def MVE_VSLIimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> { def MVE_VQSHLimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
let Inst{28} = 0b1; let Inst{28} = 0b1;
let Inst{21} = 0b1; let Inst{21} = 0b1;
} }

12
unittests/Target/ARM/MachineInstrTest.cpp
View File

@ -327,6 +327,12 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
case MVE_VQSHLU_imms16: case MVE_VQSHLU_imms16:
case MVE_VQSHLU_imms32: case MVE_VQSHLU_imms32:
case MVE_VQSHLU_imms8: case MVE_VQSHLU_imms8:
case MVE_VQSHLimms16:
case MVE_VQSHLimms32:
case MVE_VQSHLimms8:
case MVE_VQSHLimmu16:
case MVE_VQSHLimmu32:
case MVE_VQSHLimmu8:
case MVE_VQSHL_by_vecs16: case MVE_VQSHL_by_vecs16:
case MVE_VQSHL_by_vecs32: case MVE_VQSHL_by_vecs32:
case MVE_VQSHL_by_vecs8: case MVE_VQSHL_by_vecs8:
@ -411,12 +417,6 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
case MVE_VSLIimm16: case MVE_VSLIimm16:
case MVE_VSLIimm32: case MVE_VSLIimm32:
case MVE_VSLIimm8: case MVE_VSLIimm8:
case MVE_VSLIimms16:
case MVE_VSLIimms32:
case MVE_VSLIimms8:
case MVE_VSLIimmu16:
case MVE_VSLIimmu32:
case MVE_VSLIimmu8:
case MVE_VSRIimm16: case MVE_VSRIimm16:
case MVE_VSRIimm32: case MVE_VSRIimm32:
case MVE_VSRIimm8: case MVE_VSRIimm8: