RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00
Code Issues Projects Releases Wiki Activity

Add documentation for various aspects of the AMDGPU backend.

Browse Source 
Differential Revision: https://reviews.llvm.org/D33736

llvm-svn: 304831
This commit is contained in:
Tony Tye 2017-06-06 20:31:59 +00:00
parent f14b349546
commit 44bb2c5151
4 changed files with 3464 additions and 168 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3558
docs/AMDGPUUsage.rst
View File

File diff suppressed because it is too large Load Diff

59
docs/CodeGenerator.rst
View File

@ -2642,59 +2642,6 @@ to ensure valid register usage and operand types.
The AMDGPU backend
------------------
The AMDGPU code generator lives in the lib/Target/AMDGPU directory, and is an
open source native AMD GCN ISA code generator.
Target triples supported
^^^^^^^^^^^^^^^^^^^^^^^^
The following are the known target triples that are supported by the AMDGPU
backend.
* **amdgcn--** --- AMD GCN GPUs (AMDGPU.7.0.0+)
* **amdgcn--amdhsa** --- AMD GCN GPUs (AMDGPU.7.0.0+) with HSA support
* **r600--** --- AMD GPUs HD2XXX-HD6XXX
Relocations
^^^^^^^^^^^
Supported relocatable fields are:
* **word32** --- This specifies a 32-bit field occupying 4 bytes with arbitrary
byte alignment. These values use the same byte order as other word values in
the AMD GPU architecture
* **word64** --- This specifies a 64-bit field occupying 8 bytes with arbitrary
byte alignment. These values use the same byte order as other word values in
the AMD GPU architecture
Following notations are used for specifying relocation calculations:
* **A** --- Represents the addend used to compute the value of the relocatable
field
* **G** --- Represents the offset into the global offset table at which the
relocation entry’s symbol will reside during execution.
* **GOT** --- Represents the address of the global offset table.
* **P** --- Represents the place (section offset or address) of the storage unit
being relocated (computed using ``r_offset``)
* **S** --- Represents the value of the symbol whose index resides in the
relocation entry
AMDGPU Backend generates *Elf64_Rela* relocation records with the following
supported relocation types:
========================== ===== ========== ==============================
Relocation type Value Field Calculation
========================== ===== ========== ==============================
``R_AMDGPU_NONE`` 0 ``none`` ``none``
``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF
``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32
``R_AMDGPU_ABS64`` 3 ``word64`` S + A
``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
``R_AMDGPU_ABS32`` 6 ``word32`` S + A
``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P
``R_AMDGPU_GOTPCREL32_LO`` 8 ``word32`` (G + GOT + A - P) & 0xFFFFFFFF
``R_AMDGPU_GOTPCREL32_HI`` 9 ``word32`` (G + GOT + A - P) >> 32
``R_AMDGPU_REL32_LO`` 10 ``word32`` (S + A - P) & 0xFFFFFFFF
``R_AMDGPU_REL32_HI`` 11 ``word32`` (S + A - P) >> 32
========================== ===== ========== ==============================
The AMDGPU code generator lives in the ``lib/Target/AMDGPU``
directory. This code generator is capable of targeting a variety of
AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information.

11
docs/CompilerWriterInfo.rst
View File

@ -72,16 +72,7 @@ Other documents, collections, notes
AMDGPU
------
* `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`_
* `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`_
* `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf>`_
* `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf>`_
* `AMD Southern Islands Series ISA <http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf>`_
* `AMD Sea Islands Series ISA <http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf>`_
* `AMD GCN3 Instruction Set Architecture <http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf>`__
* `AMD GPU Programming Guide <http://developer.amd.com/download/AMD_Accelerated_Parallel_Processing_OpenCL_Programming_Guide.pdf>`_
* `AMD Compute Resources <http://developer.amd.com/tools/heterogeneous-computing/amd-accelerated-parallel-processing-app-sdk/documentation/>`_
* `AMDGPU Compute Application Binary Interface <https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md>`__
Refer to :doc:`AMDGPUUsage` for additional documentation.
RISC-V
------

4
docs/index.rst
View File

@ -360,10 +360,10 @@ For API clients and LLVM developers.
Answers some questions about the new Attributes infrastructure.
:doc:`NVPTXUsage`
This document describes using the NVPTX back-end to compile GPU kernels.
This document describes using the NVPTX backend to compile GPU kernels.
:doc:`AMDGPUUsage`
This document describes how to use the AMDGPU back-end.
This document describes using the AMDGPU backend to compile GPU kernels.
:doc:`StackMaps`
LLVM support for mapping instruction addresses to the location of