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Remove unused fields and arguments.
llvm-svn: 181706
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7a2df35483
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@ -78,7 +78,7 @@ static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
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if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
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return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
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} else {
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return createR600MCCodeEmitter(MCII, MRI, STI, Ctx);
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return createR600MCCodeEmitter(MCII, MRI);
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}
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}
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@ -32,9 +32,7 @@ class raw_ostream;
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extern Target TheAMDGPUTarget;
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MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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const MCRegisterInfo &MRI);
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MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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@ -35,14 +35,11 @@ class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
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void operator=(const R600MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCInstrInfo &MCII;
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const MCRegisterInfo &MRI;
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const MCSubtargetInfo &STI;
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MCContext &Ctx;
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public:
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R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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const MCSubtargetInfo &sti, MCContext &ctx)
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: MCII(mcii), MRI(mri), STI(sti), Ctx(ctx) { }
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R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
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: MCII(mcii), MRI(mri) { }
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/// \brief Encode the instruction and write it to the OS.
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virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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@ -98,10 +95,8 @@ enum TextureTypes {
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};
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MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new R600MCCodeEmitter(MCII, MRI, STI, Ctx);
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const MCRegisterInfo &MRI) {
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return new R600MCCodeEmitter(MCII, MRI);
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}
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void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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