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[X86][SSE] Fix targetShrinkDemandedConstant constant vector sign extensions

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D82257/rG3521ecf1f8a3 was incorrectly sign-extending a constant vector from the lsb, this is fine if all the constant elements are 'allsignbits' in the active bits, but if only some of the elements are, then we are corrupting the constant values for those elements.

This fix ensures we sign extend from the msb of the active/demanded bits instead.
This commit is contained in:
Simon Pilgrim 2020-07-01 12:12:34 +01:00
parent b02a489508
commit 452dc44d0b
2 changed files with 10 additions and 8 deletions
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5
lib/Target/X86/X86ISelLowering.cpp
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@ -33318,11 +33318,12 @@ X86TargetLowering::targetShrinkDemandedConstant(SDValue Op,
if (EltSize > ActiveBits && EltSize > 1 && isTypeLegal(VT) &&
(Opcode == ISD::OR || Opcode == ISD::XOR) &&
NeedsSignExtension(Op.getOperand(1), ActiveBits)) {
EVT BoolVT = EVT::getVectorVT(*TLO.DAG.getContext(), MVT::i1,
EVT ExtSVT = EVT::getIntegerVT(*TLO.DAG.getContext(), ActiveBits);
EVT ExtVT = EVT::getVectorVT(*TLO.DAG.getContext(), ExtSVT,
VT.getVectorNumElements());
SDValue NewC =
TLO.DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(Op), VT,
Op.getOperand(1), TLO.DAG.getValueType(BoolVT));
Op.getOperand(1), TLO.DAG.getValueType(ExtVT));
SDValue NewOp =
TLO.DAG.getNode(Opcode, SDLoc(Op), VT, Op.getOperand(0), NewC);
return TLO.CombineTo(Op, NewOp);

13
test/CodeGen/X86/shrink-const.ll
View File

@ -2,19 +2,20 @@
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
; FIXME: If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits
; If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits
define <4 x i32> @sext_vector_constants(<4 x i32> %a0) {
; SSE-LABEL: sext_vector_constants:
; SSE: # %bb.0:
; SSE-NEXT: pslld $17, %xmm0
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: psrld $9, %xmm0
; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
; SSE-NEXT: pslld $26, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sext_vector_constants:
; AVX: # %bb.0:
; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4227858432,4227858432,4227858432,4227858432]
; AVX-NEXT: vpslld $17, %xmm0, %xmm0
; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpsrld $9, %xmm0, %xmm0
; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpslld $26, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9>
%2 = xor <4 x i32> %1, <i32 314523200, i32 -2085372448, i32 144496960, i32 1532773600>