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Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction. llvm-svn: 84778
This commit is contained in:
Jim Grosbach
parent
23ea13afbb
commit
452de96b04
@ -341,6 +341,66 @@ namespace ARM_AM {
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return -1;
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}
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static inline unsigned getT2SOImmValRotate(unsigned V) {
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if ((V & ~255U) == 0) return 0;
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// Use CTZ to compute the rotate amount.
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unsigned RotAmt = CountTrailingZeros_32(V);
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return (32 - RotAmt) & 31;
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}
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static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
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unsigned V = Imm;
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// Passing values can be any combination of splat values and shifter
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// values. If this can be handled with a single shifter or splat, bail
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// out. Those should be handled directly, not with a two-part val.
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if (getT2SOImmValSplatVal(V) != -1)
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return false;
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V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
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if (V == 0)
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return false;
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// If this can be handled as an immediate, accept.
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if (getT2SOImmVal(V) != -1) return true;
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// Likewise, try masking out a splat value first.
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V = Imm;
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if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
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V &= ~0xff00ff00U;
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else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
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V &= ~0x00ff00ffU;
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// If what's left can be handled as an immediate, accept.
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if (getT2SOImmVal(V) != -1) return true;
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// Otherwise, do not accept.
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return false;
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}
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static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
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assert (isT2SOImmTwoPartVal(Imm) &&
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"Immedate cannot be encoded as two part immediate!");
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// Try a shifter operand as one part
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unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
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// If the rest is encodable as an immediate, then return it.
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if (getT2SOImmVal(V) != -1) return V;
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// Try masking out a splat value first.
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if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
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return Imm & 0xff00ff00U;
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// The other splat is all that's left as an option.
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assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
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return Imm & 0x00ff00ffU;
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}
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static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
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// Mask out the first hunk
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Imm ^= getT2SOImmTwoPartFirst(Imm);
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// Return what's left
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assert (getT2SOImmVal(Imm) != -1 &&
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"Unable to encode second part of T2 two part SO immediate");
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return Imm;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #2
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@ -1583,6 +1583,12 @@ def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
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def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
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(EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
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(so_imm2part_2 imm:$RHS))>;
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def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
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(ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
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(so_imm2part_2 imm:$RHS))>;
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def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
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(SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
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(so_imm2part_2 imm:$RHS))>;
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// 32-bit immediate using movw + movt.
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// This is a single pseudo instruction, the benefit is that it can be remat'd
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@ -69,6 +69,25 @@ def t2_so_imm_neg : Operand<i32>,
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return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
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}], t2_so_imm_neg_XFORM>;
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// Break t2_so_imm's up into two pieces. This handles immediates with up to 16
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// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
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// to get the first/second pieces.
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def t2_so_imm2part : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
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}]> {
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}
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def t2_so_imm2part_1 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def t2_so_imm2part_2 : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
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def imm1_31 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
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@ -1131,6 +1150,20 @@ def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
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// Non-Instruction Patterns
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//
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// Two piece so_imms.
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def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
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(t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
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(t2_so_imm2part_2 imm:$RHS))>;
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def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
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(t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
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(t2_so_imm2part_2 imm:$RHS))>;
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def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
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(t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
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(t2_so_imm2part_2 imm:$RHS))>;
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def : T2Pat<(sub GPR:$LHS, t2_so_imm2part:$RHS),
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(t2SUBri (t2SUBri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
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(t2_so_imm2part_2 imm:$RHS))>;
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// ConstantPool, GlobalAddress, and JumpTable
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def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
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def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
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@ -10,29 +10,32 @@ define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_1_fail_1:
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;CHECK: movt
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define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_2:
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;CHECK: #11206656
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;CHECK: #187
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%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_fail_2(i32 %lhs) {
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;CHECK: t2_const_var2_1_fail_2:
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;CHECK: movt
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define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_3:
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;CHECK: #11206827
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;CHECK: #16777216
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%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_fail_3(i32 %lhs) {
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;CHECK: t2_const_var2_1_fail_3:
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;CHECK: movt
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define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
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;CHECK: t2_const_var2_1_ok_4:
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;CHECK: #16777472
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;CHECK: #11206827
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%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
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ret i32 %ret
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}
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define i32 @t2_const_var2_1_fail_4(i32 %lhs) {
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;CHECK: t2_const_var2_1_fail_4:
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define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_1_fail_1:
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;CHECK: movt
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%ret = add i32 %lhs, 28027649 ; 0x01abab01
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ret i32 %ret
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@ -46,29 +49,31 @@ define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_2_fail_1:
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;CHECK: movt
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define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_2:
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;CHECK: #-1426063360
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;CHECK: #47616
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%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_fail_2(i32 %lhs) {
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;CHECK: t2_const_var2_2_fail_2:
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;CHECK: movt
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define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_3:
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;CHECK: #-1426019584
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%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_fail_3(i32 %lhs) {
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;CHECK: t2_const_var2_2_fail_3:
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;CHECK: movt
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define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
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;CHECK: t2_const_var2_2_ok_4:
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;CHECK: #-1426019584
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;CHECK: #1048592
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%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
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ret i32 %ret
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}
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define i32 @t2_const_var2_2_fail_4(i32 %lhs) {
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;CHECK: t2_const_var2_2_fail_4:
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define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
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;CHECK: t2_const_var2_2_fail_1:
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;CHECK: movt
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%ret = add i32 %lhs, 279685904 ; 0x10abab10
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ret i32 %ret
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@ -125,9 +130,10 @@ define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
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ret i32 %ret
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}
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define i32 @t2_const_var3_2_fail_1(i32 %lhs) {
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;CHECK: t2_const_var3_2_fail_1:
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;CHECK: movt
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define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
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;CHECK: t2_const_var3_2_ok_2:
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;CHECK: #2097152
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;CHECK: #1843200
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%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
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ret i32 %ret
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}
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@ -55,10 +55,10 @@ define i32 @t2MOVTi16_test_3(i32 %a) {
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define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
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; CHECK: t2MOVTi16_test_nomatch_1:
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; CHECK: movw r1, #16384
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; CHECK-NEXT: movt r1, #154
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; CHECK: #8388608
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; CHECK: movw r1, #65535
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; CHECK-NEXT: movt r1, #154
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; CHECK: #1720320
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%1 = shl i32 255, 8
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%2 = shl i32 1234, 8
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%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
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