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[InstCombine] use m_APInt to allow sub with constant folds for splat vectors

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llvm-svn: 284247
This commit is contained in:
Sanjay Patel 2016-10-14 16:31:54 +00:00
parent 23c66e03b1
commit 4538ac9f97
3 changed files with 22 additions and 23 deletions
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37
lib/Transforms/InstCombine/InstCombineAddSub.cpp
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@ -1554,34 +1554,35 @@ Instruction *InstCombiner::visitSub(BinaryOperator &I) {
return CastInst::CreateZExtOrBitCast(X, Op1->getType());
}
if (ConstantInt *C = dyn_cast<ConstantInt>(Op0)) {
const APInt *Op0C;
if (match(Op0, m_APInt(Op0C))) {
unsigned BitWidth = I.getType()->getScalarSizeInBits();
// -(X >>u 31) -> (X >>s 31)
// -(X >>s 31) -> (X >>u 31)
if (C->isZero()) {
if (*Op0C == 0) {
Value *X;
ConstantInt *CI;
if (match(Op1, m_LShr(m_Value(X), m_ConstantInt(CI))) &&
// Verify we are shifting out everything but the sign bit.
CI->getValue() == I.getType()->getPrimitiveSizeInBits() - 1)
return BinaryOperator::CreateAShr(X, CI);
if (match(Op1, m_AShr(m_Value(X), m_ConstantInt(CI))) &&
// Verify we are shifting out everything but the sign bit.
CI->getValue() == I.getType()->getPrimitiveSizeInBits() - 1)
return BinaryOperator::CreateLShr(X, CI);
const APInt *ShAmt;
if (match(Op1, m_LShr(m_Value(X), m_APInt(ShAmt))) &&
*ShAmt == BitWidth - 1) {
Value *ShAmtOp = cast<Instruction>(Op1)->getOperand(1);
return BinaryOperator::CreateAShr(X, ShAmtOp);
}
if (match(Op1, m_AShr(m_Value(X), m_APInt(ShAmt))) &&
*ShAmt == BitWidth - 1) {
Value *ShAmtOp = cast<Instruction>(Op1)->getOperand(1);
return BinaryOperator::CreateLShr(X, ShAmtOp);
}
}
// Turn this into a xor if LHS is 2^n-1 and the remaining bits are known
// zero.
APInt IntVal = C->getValue();
if ((IntVal + 1).isPowerOf2()) {
unsigned BitWidth = I.getType()->getScalarSizeInBits();
if ((*Op0C + 1).isPowerOf2()) {
APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0);
computeKnownBits(&I, KnownZero, KnownOne, 0, &I);
if ((IntVal | KnownZero).isAllOnesValue()) {
return BinaryOperator::CreateXor(Op1, C);
}
if ((*Op0C | KnownZero).isAllOnesValue())
return BinaryOperator::CreateXor(Op1, Op0);
}
}

2
test/Transforms/InstCombine/sub-xor.ll
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@ -15,7 +15,7 @@ define i32 @test1(i32 %x) {
define <2 x i32> @test1vec(<2 x i32> %x) {
; CHECK-LABEL: @test1vec(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %x, <i32 31, i32 31>
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> <i32 63, i32 63>, [[AND]]
; CHECK-NEXT: [[SUB:%.*]] = xor <2 x i32> [[AND]], <i32 63, i32 63>
; CHECK-NEXT: ret <2 x i32> [[SUB]]
;
%and = and <2 x i32> %x, <i32 31, i32 31>

6
test/Transforms/InstCombine/sub.ll
View File

@ -154,8 +154,7 @@ define i32 @test13(i32 %A) {
define <2 x i32> @test12vec(<2 x i32> %A) {
; CHECK-LABEL: @test12vec(
; CHECK-NEXT: [[B:%.*]] = ashr <2 x i32> %A, <i32 31, i32 31>
; CHECK-NEXT: [[C:%.*]] = sub nsw <2 x i32> zeroinitializer, [[B]]
; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> %A, <i32 31, i32 31>
; CHECK-NEXT: ret <2 x i32> [[C]]
;
%B = ashr <2 x i32> %A, <i32 31, i32 31>
@ -165,8 +164,7 @@ define <2 x i32> @test12vec(<2 x i32> %A) {
define <2 x i32> @test13vec(<2 x i32> %A) {
; CHECK-LABEL: @test13vec(
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i32> %A, <i32 31, i32 31>
; CHECK-NEXT: [[C:%.*]] = sub nsw <2 x i32> zeroinitializer, [[B]]
; CHECK-NEXT: [[C:%.*]] = ashr <2 x i32> %A, <i32 31, i32 31>
; CHECK-NEXT: ret <2 x i32> [[C]]
;
%B = lshr <2 x i32> %A, <i32 31, i32 31>