RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR

Browse Source 
llvm-svn: 366087
This commit is contained in:
Matt Arsenault 2019-07-15 17:26:43 +00:00
parent e16497490c
commit 455c15c8d9
2 changed files with 156 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -341,6 +341,9 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
const unsigned SrcSize = SrcTy.getSizeInBits();
if (SrcSize < 32)
return false;
const DebugLoc &DL = MI.getDebugLoc();
const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, TRI);
const unsigned DstSize = DstTy.getSizeInBits();
@ -1235,6 +1238,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
case TargetOpcode::G_EXTRACT:
return selectG_EXTRACT(I);
case TargetOpcode::G_MERGE_VALUES:
case TargetOpcode::G_BUILD_VECTOR:
case TargetOpcode::G_CONCAT_VECTORS:
return selectG_MERGE_VALUES(I);
case TargetOpcode::G_UNMERGE_VALUES:

152
test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir Normal file
View File

@ -0,0 +1,152 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
---
name: test_build_vector_v_v2s32_v_s32_v_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_v_s32
; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
S_ENDPGM 0, implicit %2
...
---
name: test_build_vector_v_v2s32_s_s32_v_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
S_ENDPGM 0, implicit %2
...
---
name: test_build_vector_v_v2s32_v_s32_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
S_ENDPGM 0, implicit %2
...
---
name: test_build_vector_s_v2s32_s_s32_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32
; GCN: liveins: $sgpr0, $sgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
S_ENDPGM 0, implicit %2
...
---
name: test_build_vector_s_v2s32_undef_s_s32_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; GCN-LABEL: name: test_build_vector_s_v2s32_undef_s_s32_s_s32
; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE undef %2:sreg_32_xm0, %subreg.sub0, [[COPY]], %subreg.sub1
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(<2 x s32>) = G_BUILD_VECTOR undef %0:sgpr(s32), %1
S_ENDPGM 0, implicit %2
...
---
name: test_build_vector_s_v2s32_s_s32_undef_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_undef_s_s32
; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[COPY]], %subreg.sub0, undef %2:sreg_32_xm0, %subreg.sub1
; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
%0:sgpr(s32) = COPY $sgpr0
%2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, undef %1:sgpr(s32),
S_ENDPGM 0, implicit %2
...
---
name: test_build_vector_s_v2s64_s_s64_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64
; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = COPY $sgpr2_sgpr3
%4:sgpr(<2 x s64>) = G_BUILD_VECTOR %0, %1
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
...