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Add icache prefetch operations to AArch64

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This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.

llvm-svn: 174495
This commit is contained in:
Tim Northover 2013-02-06 09:04:56 +00:00
parent 2da9899378
commit 45bdd458aa
4 changed files with 62 additions and 0 deletions
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6
lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
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@ -120,6 +120,12 @@ const NamedImmMapper::Mapping A64PRFM::PRFMMapper::PRFMPairs[] = {
{"pldl2strm", PLDL2STRM}, {"pldl2strm", PLDL2STRM},
{"pldl3keep", PLDL3KEEP}, {"pldl3keep", PLDL3KEEP},
{"pldl3strm", PLDL3STRM}, {"pldl3strm", PLDL3STRM},
{"plil1keep", PLIL1KEEP},
{"plil1strm", PLIL1STRM},
{"plil2keep", PLIL2KEEP},
{"plil2strm", PLIL2STRM},
{"plil3keep", PLIL3KEEP},
{"plil3strm", PLIL3STRM},
{"pstl1keep", PSTL1KEEP}, {"pstl1keep", PSTL1KEEP},
{"pstl1strm", PSTL1STRM}, {"pstl1strm", PSTL1STRM},
{"pstl2keep", PSTL2KEEP}, {"pstl2keep", PSTL2KEEP},

6
lib/Target/AArch64/Utils/AArch64BaseInfo.h
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@ -248,6 +248,12 @@ namespace A64PRFM {
PLDL2STRM = 0x03, PLDL2STRM = 0x03,
PLDL3KEEP = 0x04, PLDL3KEEP = 0x04,
PLDL3STRM = 0x05, PLDL3STRM = 0x05,
PLIL1KEEP = 0x08,
PLIL1STRM = 0x09,
PLIL2KEEP = 0x0a,
PLIL2STRM = 0x0b,
PLIL3KEEP = 0x0c,
PLIL3STRM = 0x0d,
PSTL1KEEP = 0x10, PSTL1KEEP = 0x10,
PSTL1STRM = 0x11, PSTL1STRM = 0x11,
PSTL2KEEP = 0x12, PSTL2KEEP = 0x12,

12
test/MC/AArch64/basic-a64-instructions.s
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@ -2423,6 +2423,12 @@ _func:
prfm pldl2strm, [x2] prfm pldl2strm, [x2]
prfm pldl3keep, [x5] prfm pldl3keep, [x5]
prfm pldl3strm, [x6] prfm pldl3strm, [x6]
prfm plil1keep, [sp, #8]
prfm plil1strm, [x3]
prfm plil2keep, [x5,#16]
prfm plil2strm, [x2]
prfm plil3keep, [x5]
prfm plil3strm, [x6]
prfm pstl1keep, [sp, #8] prfm pstl1keep, [sp, #8]
prfm pstl1strm, [x3] prfm pstl1strm, [x3]
prfm pstl2keep, [x5,#16] prfm pstl2keep, [x5,#16]
@ -2436,6 +2442,12 @@ _func:
// CHECK: prfm pldl2strm, [x2, #0] // encoding: [0x43,0x00,0x80,0xf9] // CHECK: prfm pldl2strm, [x2, #0] // encoding: [0x43,0x00,0x80,0xf9]
// CHECK: prfm pldl3keep, [x5, #0] // encoding: [0xa4,0x00,0x80,0xf9] // CHECK: prfm pldl3keep, [x5, #0] // encoding: [0xa4,0x00,0x80,0xf9]
// CHECK: prfm pldl3strm, [x6, #0] // encoding: [0xc5,0x00,0x80,0xf9] // CHECK: prfm pldl3strm, [x6, #0] // encoding: [0xc5,0x00,0x80,0xf9]
// CHECK: prfm plil1keep, [sp, #8] // encoding: [0xe8,0x07,0x80,0xf9]
// CHECK: prfm plil1strm, [x3, #0] // encoding: [0x69,0x00,0x80,0xf9]
// CHECK: prfm plil2keep, [x5, #16] // encoding: [0xaa,0x08,0x80,0xf9]
// CHECK: prfm plil2strm, [x2, #0] // encoding: [0x4b,0x00,0x80,0xf9]
// CHECK: prfm plil3keep, [x5, #0] // encoding: [0xac,0x00,0x80,0xf9]
// CHECK: prfm plil3strm, [x6, #0] // encoding: [0xcd,0x00,0x80,0xf9]
// CHECK: prfm pstl1keep, [sp, #8] // encoding: [0xf0,0x07,0x80,0xf9] // CHECK: prfm pstl1keep, [sp, #8] // encoding: [0xf0,0x07,0x80,0xf9]
// CHECK: prfm pstl1strm, [x3, #0] // encoding: [0x71,0x00,0x80,0xf9] // CHECK: prfm pstl1strm, [x3, #0] // encoding: [0x71,0x00,0x80,0xf9]
// CHECK: prfm pstl2keep, [x5, #16] // encoding: [0xb2,0x08,0x80,0xf9] // CHECK: prfm pstl2keep, [x5, #16] // encoding: [0xb2,0x08,0x80,0xf9]

38
test/MC/Disassembler/AArch64/basic-a64-instructions.txt
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@ -2335,6 +2335,44 @@
0x43 0xfd 0x7f 0xfd 0x43 0xfd 0x7f 0xfd
0xec 0xff 0xbf 0x3d 0xec 0xff 0xbf 0x3d
# CHECK: prfm pldl1keep, [sp, #8]
# CHECK: prfm pldl1strm, [x3, #0]
# CHECK: prfm pldl2keep, [x5, #16]
# CHECK: prfm pldl2strm, [x2, #0]
# CHECK: prfm pldl3keep, [x5, #0]
# CHECK: prfm pldl3strm, [x6, #0]
# CHECK: prfm plil1keep, [sp, #8]
# CHECK: prfm plil1strm, [x3, #0]
# CHECK: prfm plil2keep, [x5, #16]
# CHECK: prfm plil2strm, [x2, #0]
# CHECK: prfm plil3keep, [x5, #0]
# CHECK: prfm plil3strm, [x6, #0]
# CHECK: prfm pstl1keep, [sp, #8]
# CHECK: prfm pstl1strm, [x3, #0]
# CHECK: prfm pstl2keep, [x5, #16]
# CHECK: prfm pstl2strm, [x2, #0]
# CHECK: prfm pstl3keep, [x5, #0]
# CHECK: prfm pstl3strm, [x6, #0]
0xe0 0x07 0x80 0xf9
0x61 0x00 0x80 0xf9
0xa2 0x08 0x80 0xf9
0x43 0x00 0x80 0xf9
0xa4 0x00 0x80 0xf9
0xc5 0x00 0x80 0xf9
0xe8 0x07 0x80 0xf9
0x69 0x00 0x80 0xf9
0xaa 0x08 0x80 0xf9
0x4b 0x00 0x80 0xf9
0xac 0x00 0x80 0xf9
0xcd 0x00 0x80 0xf9
0xf0 0x07 0x80 0xf9
0x71 0x00 0x80 0xf9
0xb2 0x08 0x80 0xf9
0x53 0x00 0x80 0xf9
0xb4 0x00 0x80 0xf9
0xd5 0x00 0x80 0xf9
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Load/store (register offset) # Load/store (register offset)
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------