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[AMDGPU] Add alignment check for v3 to v4 load type promotion
It should be enabled only when the load alignment is at least 8-byte. Fixes: SWDEV-256824 Reviewed By: foad Differential Revision: https://reviews.llvm.org/D90404
This commit is contained in:
Christudasan Devadasan
parent
0536175cbb
commit
45dd9c1c1d
@ -7986,6 +7986,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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LoadSDNode *Load = cast<LoadSDNode>(Op);
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ISD::LoadExtType ExtType = Load->getExtensionType();
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EVT MemVT = Load->getMemoryVT();
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MachineMemOperand *MMO = Load->getMemOperand();
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if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
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if (MemVT == MVT::i16 && isTypeLegal(MVT::i16))
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@ -7996,7 +7997,6 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Load->getChain();
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SDValue BasePtr = Load->getBasePtr();
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MachineMemOperand *MMO = Load->getMemOperand();
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EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
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@ -8052,13 +8052,15 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
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unsigned NumElements = MemVT.getVectorNumElements();
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bool Is16ByteKnownDereferenceable = MMO->getPointerInfo().isDereferenceable(
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16, *DAG.getContext(), DAG.getDataLayout());
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if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
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AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
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if (!Op->isDivergent() && Alignment >= 4 && NumElements < 32) {
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if (MemVT.isPow2VectorType())
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return SDValue();
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if (NumElements == 3)
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if (NumElements == 3 && (Alignment >= 8 || Is16ByteKnownDereferenceable))
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return WidenVectorLoad(Op, DAG);
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return SplitVectorLoad(Op, DAG);
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}
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@ -8076,7 +8078,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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Alignment >= 4 && NumElements < 32) {
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if (MemVT.isPow2VectorType())
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return SDValue();
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if (NumElements == 3)
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if (NumElements == 3 && (Alignment >= 8 || Is16ByteKnownDereferenceable))
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return WidenVectorLoad(Op, DAG);
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return SplitVectorLoad(Op, DAG);
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}
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@ -8092,8 +8094,11 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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if (NumElements > 4)
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return SplitVectorLoad(Op, DAG);
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// v3 loads not supported on SI.
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if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores())
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return WidenVectorLoad(Op, DAG);
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if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores()) {
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if (Alignment >= 8 || Is16ByteKnownDereferenceable)
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return WidenVectorLoad(Op, DAG);
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return SplitVectorLoad(Op, DAG);
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}
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// v3 and v4 loads are supported for private and global memory.
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return SDValue();
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}
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@ -8116,8 +8121,11 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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if (NumElements > 4)
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return SplitVectorLoad(Op, DAG);
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// v3 loads not supported on SI.
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if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores())
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return WidenVectorLoad(Op, DAG);
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if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores()) {
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if (Alignment >= 8 || Is16ByteKnownDereferenceable)
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return WidenVectorLoad(Op, DAG);
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return SplitVectorLoad(Op, DAG);
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}
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return SDValue();
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default:
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llvm_unreachable("unsupported private_element_size");
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@ -8,8 +8,8 @@
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; FUNC-LABEL: {{^}}bfi_def:
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; R600: BFI_INT
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; GCN: s_andn2_b32
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; GCN: s_and_b32
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; GCN-DAG: s_andn2_b32
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; GCN-DAG: s_and_b32
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; GCN: s_or_b32
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define amdgpu_kernel void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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@ -12,14 +12,15 @@ define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
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; SI-LABEL: fshl_i32:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
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; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
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; SI-NEXT: s_load_dword s0, s[0:1], 0xd
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, s1
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; SI-NEXT: s_lshr_b32 s1, s0, 1
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; SI-NEXT: v_alignbit_b32 v0, s0, v0, 1
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; SI-NEXT: s_not_b32 s0, s2
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; SI-NEXT: v_mov_b32_e32 v0, s3
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; SI-NEXT: s_not_b32 s0, s0
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; SI-NEXT: v_alignbit_b32 v0, s2, v0, 1
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; SI-NEXT: s_lshr_b32 s1, s2, 1
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; SI-NEXT: v_mov_b32_e32 v1, s0
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; SI-NEXT: v_alignbit_b32 v0, s1, v0, v1
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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@ -27,33 +28,35 @@ define amdgpu_kernel void @fshl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
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;
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; VI-LABEL: fshl_i32:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
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; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
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; VI-NEXT: s_load_dword s0, s[0:1], 0x34
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s1
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; VI-NEXT: s_not_b32 s2, s2
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; VI-NEXT: s_lshr_b32 s1, s0, 1
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; VI-NEXT: v_alignbit_b32 v0, s0, v0, 1
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; VI-NEXT: v_mov_b32_e32 v1, s2
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; VI-NEXT: v_mov_b32_e32 v0, s5
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; VI-NEXT: s_not_b32 s0, s0
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; VI-NEXT: s_lshr_b32 s1, s4, 1
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; VI-NEXT: v_alignbit_b32 v0, s4, v0, 1
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; VI-NEXT: v_mov_b32_e32 v1, s0
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; VI-NEXT: v_alignbit_b32 v2, s1, v0, v1
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: v_mov_b32_e32 v0, s2
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: fshl_i32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
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; GFX9-NEXT: s_load_dword s0, s[0:1], 0x34
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: s_not_b32 s2, s2
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; GFX9-NEXT: s_lshr_b32 s1, s0, 1
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; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 1
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; GFX9-NEXT: v_mov_b32_e32 v1, s2
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; GFX9-NEXT: v_mov_b32_e32 v0, s5
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; GFX9-NEXT: s_not_b32 s0, s0
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; GFX9-NEXT: s_lshr_b32 s1, s4, 1
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; GFX9-NEXT: v_alignbit_b32 v0, s4, v0, 1
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; GFX9-NEXT: v_mov_b32_e32 v1, s0
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; GFX9-NEXT: v_alignbit_b32 v2, s1, v0, v1
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: v_mov_b32_e32 v1, s5
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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@ -21,39 +21,42 @@ define amdgpu_kernel void @fshr_i32(i32 addrspace(1)* %in, i32 %x, i32 %y, i32 %
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; SI-LABEL: fshr_i32:
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; SI: ; %bb.0: ; %entry
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; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
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; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
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; SI-NEXT: s_load_dword s0, s[0:1], 0xd
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, s1
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; SI-NEXT: v_mov_b32_e32 v1, s2
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; SI-NEXT: v_alignbit_b32 v0, s0, v0, v1
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; SI-NEXT: v_mov_b32_e32 v0, s3
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; SI-NEXT: v_mov_b32_e32 v1, s0
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; SI-NEXT: v_alignbit_b32 v0, s2, v0, v1
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: fshr_i32:
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; VI: ; %bb.0: ; %entry
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; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
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; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
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; VI-NEXT: s_load_dword s0, s[0:1], 0x34
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s1
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; VI-NEXT: v_mov_b32_e32 v1, s2
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; VI-NEXT: v_alignbit_b32 v2, s0, v0, v1
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: v_mov_b32_e32 v1, s5
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; VI-NEXT: v_mov_b32_e32 v0, s5
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; VI-NEXT: v_mov_b32_e32 v1, s0
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; VI-NEXT: v_alignbit_b32 v2, s4, v0, v1
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; VI-NEXT: v_mov_b32_e32 v0, s2
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX9-LABEL: fshr_i32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
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; GFX9-NEXT: s_load_dword s0, s[0:1], 0x34
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s1
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; GFX9-NEXT: v_mov_b32_e32 v1, s2
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; GFX9-NEXT: v_alignbit_b32 v2, s0, v0, v1
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: v_mov_b32_e32 v1, s5
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; GFX9-NEXT: v_mov_b32_e32 v0, s5
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; GFX9-NEXT: v_mov_b32_e32 v1, s0
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; GFX9-NEXT: v_alignbit_b32 v2, s4, v0, v1
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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@ -275,7 +275,8 @@ define amdgpu_kernel void @merge_global_store_4_adjacent_loads_i32(i32 addrspace
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}
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; GCN-LABEL: {{^}}merge_global_store_3_adjacent_loads_i32:
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; SI-DAG: buffer_load_dwordx4
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; SI-DAG: buffer_load_dwordx2
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; SI-DAG: buffer_load_dword
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; CI-DAG: buffer_load_dwordx3
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; GCN: s_waitcnt
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; SI-DAG: buffer_store_dwordx2
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@ -613,7 +614,8 @@ define amdgpu_kernel void @merge_global_store_8_constants_i32(i32 addrspace(1)*
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; GCN-LABEL: {{^}}copy_v3i32_align4:
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; GCN-NOT: SCRATCH_RSRC_DWORD
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; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
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; CI-DAG: buffer_load_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-NOT: offen
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; GCN: s_waitcnt vmcnt
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@ -647,7 +649,8 @@ define amdgpu_kernel void @copy_v3i64_align4(<3 x i64> addrspace(1)* noalias %ou
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; GCN-LABEL: {{^}}copy_v3f32_align4:
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; GCN-NOT: SCRATCH_RSRC_DWORD
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; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
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; CI-DAG: buffer_load_dwordx3 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GCN-NOT: offen
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; GCN: s_waitcnt vmcnt
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71
test/CodeGen/AMDGPU/promote-vect3-load.ll
Normal file
71
test/CodeGen/AMDGPU/promote-vect3-load.ll
Normal file
@ -0,0 +1,71 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; The type promotion for the vector loads v3i32/v3f32 into v4i32/v4f32 is enabled
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; only when the alignment is 8-byte or higher.
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; Otherwise, split the load into two separate loads (dwordx2 + dword).
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; This type promotion on smaller aligned loads can cause a page fault error
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; while accessing one extra dword beyond the buffer.
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define protected amdgpu_kernel void @load_v3i32_align4(<3 x i32> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3i32_align4:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[0:1], 0x8
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 4
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store <3 x i32> %vec, <3 x i32> addrspace(1)* undef, align 4
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ret void
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}
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define protected amdgpu_kernel void @load_v3i32_align8(<3 x i32> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3i32_align8:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 8
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store <3 x i32> %vec, <3 x i32> addrspace(1)* undef, align 8
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ret void
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}
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define protected amdgpu_kernel void @load_v3i32_align16(<3 x i32> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3i32_align16:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
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store <3 x i32> %vec, <3 x i32> addrspace(1)* undef, align 16
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ret void
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}
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define protected amdgpu_kernel void @load_v3f32_align4(<3 x float> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3f32_align4:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[0:1], 0x8
|
||||
%vec = load <3 x float>, <3 x float> addrspace(1)* %arg, align 4
|
||||
store <3 x float> %vec, <3 x float> addrspace(1)* undef, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define protected amdgpu_kernel void @load_v3f32_align8(<3 x float> addrspace(1)* %arg) #0 {
|
||||
; GCN-LABEL: load_v3f32_align8:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
|
||||
%vec = load <3 x float>, <3 x float> addrspace(1)* %arg, align 8
|
||||
store <3 x float> %vec, <3 x float> addrspace(1)* undef, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define protected amdgpu_kernel void @load_v3f32_align16(<3 x float> addrspace(1)* %arg) #0 {
|
||||
; GCN-LABEL: load_v3f32_align16:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
|
||||
%vec = load <3 x float>, <3 x float> addrspace(1)* %arg, align 16
|
||||
store <3 x float> %vec, <3 x float> addrspace(1)* undef, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind noinline }
|
||||
@ -38,30 +38,32 @@ define amdgpu_kernel void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a
|
||||
; SI-LABEL: test_s_sext_i32_to_i64:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
|
||||
; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
|
||||
; SI-NEXT: s_load_dword s0, s[0:1], 0xd
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mul_i32 s0, s0, s1
|
||||
; SI-NEXT: s_add_i32 s0, s0, s2
|
||||
; SI-NEXT: s_ashr_i32 s1, s0, 31
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s0
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s1
|
||||
; SI-NEXT: s_mul_i32 s1, s2, s3
|
||||
; SI-NEXT: s_add_i32 s1, s1, s0
|
||||
; SI-NEXT: s_ashr_i32 s0, s1, 31
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s1
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s0
|
||||
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_s_sext_i32_to_i64:
|
||||
; VI: ; %bb.0: ; %entry
|
||||
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
|
||||
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
|
||||
; VI-NEXT: s_load_dword s0, s[0:1], 0x34
|
||||
; VI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s6, -1
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_mul_i32 s0, s0, s1
|
||||
; VI-NEXT: s_add_i32 s0, s0, s2
|
||||
; VI-NEXT: s_ashr_i32 s1, s0, 31
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s1
|
||||
; VI-NEXT: s_mul_i32 s1, s2, s3
|
||||
; VI-NEXT: s_add_i32 s1, s1, s0
|
||||
; VI-NEXT: s_ashr_i32 s0, s1, 31
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s1
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s0
|
||||
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
entry:
|
||||
@ -290,13 +292,14 @@ define amdgpu_kernel void @v_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32
|
||||
; SI-LABEL: v_sext_i1_to_i16_with_and:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb
|
||||
; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb
|
||||
; SI-NEXT: s_load_dword s0, s[0:1], 0xd
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s2
|
||||
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], s1, v0
|
||||
; SI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s0
|
||||
; SI-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v0
|
||||
; SI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
|
||||
; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
|
||||
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
||||
@ -305,13 +308,14 @@ define amdgpu_kernel void @v_sext_i1_to_i16_with_and(i16 addrspace(1)* %out, i32
|
||||
; VI-LABEL: v_sext_i1_to_i16_with_and:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
|
||||
; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
|
||||
; VI-NEXT: s_load_dword s0, s[0:1], 0x34
|
||||
; VI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; VI-NEXT: s_mov_b32 s6, -1
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v0
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s2
|
||||
; VI-NEXT: v_cmp_eq_u32_e64 s[0:1], s1, v0
|
||||
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s2, v0
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s0
|
||||
; VI-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v0
|
||||
; VI-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
|
||||
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
|
||||
; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
|
||||
|
||||
@ -34,35 +34,37 @@ define amdgpu_kernel void @extract_insert_same_dynelt_v4i32(i32 addrspace(1)* %o
|
||||
define amdgpu_kernel void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 {
|
||||
; GCN-LABEL: extract_insert_different_dynelt_v4i32:
|
||||
; GCN: ; %bb.0:
|
||||
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
|
||||
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
||||
; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, 0
|
||||
; GCN-NEXT: s_mov_b32 s3, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s2, 0
|
||||
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-NEXT: s_mov_b32 s6, 0
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
|
||||
; GCN-NEXT: s_mov_b64 s[4:5], s[10:11]
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
|
||||
; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[0:3], 0 addr64
|
||||
; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[4:7], 0 addr64
|
||||
; GCN-NEXT: s_load_dword s0, s[0:1], 0xf
|
||||
; GCN-NEXT: v_lshlrev_b32_e32 v6, 2, v0
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s8
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 3
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, s2
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 3
|
||||
; GCN-NEXT: v_mov_b32_e32 v7, v5
|
||||
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
|
||||
; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 2
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 2
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 1
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 1
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 2
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s10, 3
|
||||
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
|
||||
; GCN-NEXT: buffer_store_dword v0, v[6:7], s[4:7], 0 addr64
|
||||
; GCN-NEXT: buffer_store_dword v0, v[6:7], s[8:11], 0 addr64
|
||||
; GCN-NEXT: s_endpgm
|
||||
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%id.ext = sext i32 %id to i64
|
||||
|
||||
Loading…
Reference in New Issue
Block a user