RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Code Issues Projects Releases Wiki Activity

Remove an incorrect overaggressive optimization

Browse Source 
(PPC specific).

llvm-svn: 89496
This commit is contained in:
Dale Johannesen 2009-11-20 22:16:40 +00:00
parent d92626fc0d
commit 45f80d39f6
2 changed files with 31 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -443,8 +443,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
unsigned MB, ME; unsigned MB, ME;
if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
SDValue Tmp1, Tmp2, Tmp3; SDValue Tmp1, Tmp2;
bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
isInt32Immediate(Op1.getOperand(1), Value)) { isInt32Immediate(Op1.getOperand(1), Value)) {
@ -462,9 +461,8 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
} }
} }
Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
SH &= 31; SH &= 31;
SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) }; getI32Imm(ME) };
return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
} }

28
test/CodeGen/PowerPC/rlwimi-keep-rsh.ll Normal file
View File

@ -0,0 +1,28 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s
; Formerly dropped the RHS of %tmp6 when constructing rlwimi.
; 7346117
@foo = external global i32
define void @xxx(i32 %a, i32 %b, i32 %c, i32 %d) nounwind optsize {
; CHECK: _xxx:
; CHECK: or
; CHECK: and
; CHECK: rlwimi
entry:
%tmp0 = ashr i32 %d, 31
%tmp1 = and i32 %tmp0, 255
%tmp2 = xor i32 %tmp1, 255
%tmp3 = ashr i32 %b, 31
%tmp4 = ashr i32 %a, 4
%tmp5 = or i32 %tmp3, %tmp4
%tmp6 = and i32 %tmp2, %tmp5
%tmp7 = shl i32 %c, 8
%tmp8 = or i32 %tmp6, %tmp7
store i32 %tmp8, i32* @foo, align 4
br label %return
return:
ret void
; CHECK: blr
}