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[X86][SSE] Remove XFormVExtractWithShuffleIntoLoad to prevent legalization infinite loops (PR43971)
As detailed in PR43971/D70267, the use of XFormVExtractWithShuffleIntoLoad causes issues where we end up in infinite loops of extract(targetshuffle(vecload)) -> extract(shuffle(vecload)) -> extract(vecload) -> extract(targetshuffle(vecload)), there are just too many legalization checks at every stage that we can't guarantee that extract(shuffle(vecload)) -> scalarload can occur. At the moment we see a number of minor regressions as we don't fold extract(shuffle(vecload)) -> scalarload before legal ops, these can be addressed in future patches and extension of X86ISelLowering's combineExtractWithShuffle.
This commit is contained in:
Simon Pilgrim
parent
646f60afdf
commit
46989d6a40
@ -35126,123 +35126,6 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
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Op, DemandedBits, DemandedElts, DAG, Depth);
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}
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/// Check if a vector extract from a target-specific shuffle of a load can be
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/// folded into a single element load.
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/// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
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/// shuffles have been custom lowered so we need to handle those here.
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static SDValue
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XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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SDValue InVec = N->getOperand(0);
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SDValue EltNo = N->getOperand(1);
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EVT EltVT = N->getValueType(0);
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if (!isa<ConstantSDNode>(EltNo))
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return SDValue();
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EVT OriginalVT = InVec.getValueType();
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unsigned NumOriginalElts = OriginalVT.getVectorNumElements();
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// Peek through bitcasts, don't duplicate a load with other uses.
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InVec = peekThroughOneUseBitcasts(InVec);
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EVT CurrentVT = InVec.getValueType();
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if (!CurrentVT.isVector())
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return SDValue();
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unsigned NumCurrentElts = CurrentVT.getVectorNumElements();
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if ((NumOriginalElts % NumCurrentElts) != 0)
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return SDValue();
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if (!isTargetShuffle(InVec.getOpcode()))
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return SDValue();
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// Don't duplicate a load with other uses.
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if (!InVec.hasOneUse())
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return SDValue();
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SmallVector<int, 16> ShuffleMask;
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SmallVector<SDValue, 2> ShuffleOps;
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bool UnaryShuffle;
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if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(), true,
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ShuffleOps, ShuffleMask, UnaryShuffle))
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return SDValue();
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unsigned Scale = NumOriginalElts / NumCurrentElts;
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if (Scale > 1) {
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SmallVector<int, 16> ScaledMask;
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scaleShuffleMask<int>(Scale, ShuffleMask, ScaledMask);
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ShuffleMask = std::move(ScaledMask);
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}
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assert(ShuffleMask.size() == NumOriginalElts && "Shuffle mask size mismatch");
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// Select the input vector, guarding against out of range extract vector.
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int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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int Idx = (Elt > (int)NumOriginalElts) ? SM_SentinelUndef : ShuffleMask[Elt];
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if (Idx == SM_SentinelZero)
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return EltVT.isInteger() ? DAG.getConstant(0, SDLoc(N), EltVT)
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: DAG.getConstantFP(+0.0, SDLoc(N), EltVT);
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if (Idx == SM_SentinelUndef)
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return DAG.getUNDEF(EltVT);
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// Bail if any mask element is SM_SentinelZero - getVectorShuffle below
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// won't handle it.
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if (llvm::any_of(ShuffleMask, [](int M) { return M == SM_SentinelZero; }))
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return SDValue();
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assert(0 <= Idx && Idx < (int)(2 * NumOriginalElts) &&
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"Shuffle index out of range");
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SDValue LdNode = (Idx < (int)NumOriginalElts) ? ShuffleOps[0] : ShuffleOps[1];
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// If inputs to shuffle are the same for both ops, then allow 2 uses
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unsigned AllowedUses =
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(ShuffleOps.size() > 1 && ShuffleOps[0] == ShuffleOps[1]) ? 2 : 1;
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if (LdNode.getOpcode() == ISD::BITCAST) {
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// Don't duplicate a load with other uses.
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if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
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return SDValue();
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AllowedUses = 1; // only allow 1 load use if we have a bitcast
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LdNode = LdNode.getOperand(0);
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}
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if (!ISD::isNormalLoad(LdNode.getNode()))
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return SDValue();
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LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
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if (!LN0 || !LN0->hasNUsesOfValue(AllowedUses, 0) || !LN0->isSimple())
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return SDValue();
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// If there's a bitcast before the shuffle, check if the load type and
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// alignment is valid.
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unsigned Align = LN0->getAlignment();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
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EltVT.getTypeForEVT(*DAG.getContext()));
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if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
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return SDValue();
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// All checks match so transform back to vector_shuffle so that DAG combiner
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// can finish the job
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SDLoc dl(N);
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// Create shuffle node taking into account the case that its a unary shuffle
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SDValue Shuffle = UnaryShuffle ? DAG.getUNDEF(OriginalVT)
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: DAG.getBitcast(OriginalVT, ShuffleOps[1]);
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Shuffle = DAG.getVectorShuffle(OriginalVT, dl,
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DAG.getBitcast(OriginalVT, ShuffleOps[0]),
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Shuffle, ShuffleMask);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
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EltNo);
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}
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// Helper to peek through bitops/setcc to determine size of source vector.
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// Allows combineBitcastvxi1 to determine what size vector generated a <X x i1>.
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static bool checkBitcastSrcVectorSize(SDValue Src, unsigned Size) {
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@ -36496,14 +36379,11 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
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}
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// TODO - Remove this once we can handle the implicit zero-extension of
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// X86ISD::PEXTRW/X86ISD::PEXTRB in XFormVExtractWithShuffleIntoLoad,
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// combineHorizontalPredicateResult and combineBasicSADPattern.
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// X86ISD::PEXTRW/X86ISD::PEXTRB in combineHorizontalPredicateResult and
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// combineBasicSADPattern.
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return SDValue();
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}
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if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
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return NewOp;
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// Detect mmx extraction of all bits as a i64. It works better as a bitcast.
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if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
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VT == MVT::i64 && SrcVT == MVT::v1i64 && isNullConstant(EltIdx)) {
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@ -5,15 +5,21 @@
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define float @test(<4 x float>* %A) nounwind {
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; X86-LABEL: test:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: flds 12(%eax)
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; X86-NEXT: movaps %xmm0, (%eax)
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; X86-NEXT: movaps (%eax), %xmm0
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; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X86-NEXT: xorps %xmm1, %xmm1
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; X86-NEXT: movaps %xmm1, (%eax)
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; X86-NEXT: movss %xmm0, (%esp)
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; X86-NEXT: flds (%esp)
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; X86-NEXT: popl %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: movaps (%rdi), %xmm0
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; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X64-NEXT: xorps %xmm1, %xmm1
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; X64-NEXT: movaps %xmm1, (%rdi)
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; X64-NEXT: retq
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@ -9,13 +9,20 @@ define i32 @t(<2 x i64>* %val) nounwind {
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; X32-SSE2-LABEL: t:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movl 8(%eax), %eax
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,0,1]
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; X32-SSE2-NEXT: movd %xmm0, %eax
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; X32-SSE2-NEXT: retl
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;
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; X64-LABEL: t:
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; X64: # %bb.0:
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; X64-NEXT: movl 8(%rdi), %eax
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; X64-NEXT: retq
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; X64-SSSE3-LABEL: t:
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; X64-SSSE3: # %bb.0:
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; X64-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,0,1]
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; X64-SSSE3-NEXT: movd %xmm0, %eax
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: t:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: movl 8(%rdi), %eax
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; X64-AVX-NEXT: retq
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%tmp2 = load <2 x i64>, <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
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%tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
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@ -127,7 +134,8 @@ define float @t6(<8 x float> *%a0) {
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; X32-SSE2-NEXT: pushl %eax
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; X32-SSE2-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-SSE2-NEXT: movaps (%eax), %xmm0
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; X32-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; X32-SSE2-NEXT: xorps %xmm1, %xmm1
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; X32-SSE2-NEXT: cmpeqss %xmm0, %xmm1
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; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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@ -142,7 +150,7 @@ define float @t6(<8 x float> *%a0) {
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;
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; X64-SSSE3-LABEL: t6:
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; X64-SSSE3: # %bb.0:
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: movshdup {{.*#+}} xmm1 = mem[1,1,3,3]
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; X64-SSSE3-NEXT: xorps %xmm0, %xmm0
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; X64-SSSE3-NEXT: cmpeqss %xmm1, %xmm0
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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@ -165,3 +173,50 @@ define float @t6(<8 x float> *%a0) {
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%cond = select i1 %cmp, float 1.000000e+00, float %vecext
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ret float %cond
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}
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define void @PR43971(<8 x float> *%a0, float *%a1) {
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; X32-SSE2-LABEL: PR43971:
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; X32-SSE2: # %bb.0: # %entry
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: movaps 16(%ecx), %xmm0
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; X32-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; X32-SSE2-NEXT: xorps %xmm1, %xmm1
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; X32-SSE2-NEXT: cmpltss %xmm0, %xmm1
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; X32-SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X32-SSE2-NEXT: andps %xmm1, %xmm2
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; X32-SSE2-NEXT: andnps %xmm0, %xmm1
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; X32-SSE2-NEXT: orps %xmm2, %xmm1
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; X32-SSE2-NEXT: movss %xmm1, (%eax)
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; X32-SSE2-NEXT: retl
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;
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; X64-SSSE3-LABEL: PR43971:
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; X64-SSSE3: # %bb.0: # %entry
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: xorps %xmm1, %xmm1
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; X64-SSSE3-NEXT: cmpltss %xmm0, %xmm1
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; X64-SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-SSSE3-NEXT: andps %xmm1, %xmm2
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; X64-SSSE3-NEXT: andnps %xmm0, %xmm1
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; X64-SSSE3-NEXT: orps %xmm2, %xmm1
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; X64-SSSE3-NEXT: movss %xmm1, (%rsi)
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; X64-SSSE3-NEXT: retq
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;
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; X64-AVX-LABEL: PR43971:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vpermilpd {{.*#+}} xmm0 = mem[1,0]
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; X64-AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; X64-AVX-NEXT: vcmpltss %xmm0, %xmm1, %xmm1
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; X64-AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; X64-AVX-NEXT: vmovss %xmm0, (%rsi)
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; X64-AVX-NEXT: retq
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entry:
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%0 = load <8 x float>, <8 x float>* %a0, align 32
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%vecext = extractelement <8 x float> %0, i32 6
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%cmp = fcmp ogt float %vecext, 0.000000e+00
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%1 = load float, float* %a1, align 4
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%cond = select i1 %cmp, float %1, float %vecext
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store float %cond, float* %a1, align 4
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ret void
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}
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@ -269,12 +269,12 @@ define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) {
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define float @extract_lane_insertps_5123(<4 x float> %a0, <4 x float> *%p1) {
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; SSE-LABEL: extract_lane_insertps_5123:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: movshdup {{.*#+}} xmm0 = mem[1,1,3,3]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: extract_lane_insertps_5123:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: vmovshdup {{.*#+}} xmm0 = mem[1,1,3,3]
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; AVX-NEXT: retq
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%a1 = load <4 x float>, <4 x float> *%p1
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 64)
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@ -285,12 +285,13 @@ define float @extract_lane_insertps_5123(<4 x float> %a0, <4 x float> *%p1) {
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define float @extract_lane_insertps_6123(<4 x float> %a0, <4 x float> *%p1) {
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; SSE-LABEL: extract_lane_insertps_6123:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: movaps (%rdi), %xmm0
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; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: extract_lane_insertps_6123:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: vpermilpd {{.*#+}} xmm0 = mem[1,0]
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; AVX-NEXT: retq
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%a1 = load <4 x float>, <4 x float> *%p1
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 128)
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@ -57,13 +57,15 @@ define void @test3(float* %R, <4 x float>* %P1) nounwind {
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-NEXT: movaps (%ecx), %xmm0
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; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X32-NEXT: movss %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: movaps (%rsi), %xmm0
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; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X64-NEXT: movss %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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