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[Power9]Legalize and emit code for round & convert quad-precision values
Legalize and emit code for round & convert float128 to double precision and single precision. Differential Revision: https://reviews.llvm.org/D46997 llvm-svn: 336299
This commit is contained in:
Lei Huang
parent
1415773fba
commit
46c288db0b
@ -515,7 +515,8 @@ def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
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XSRSQRTESP,
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XSSUBDP,
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XSSUBSP,
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XSCVDPSPN
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XSCVDPSPN,
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XSRSP
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)>;
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// Three Cycle PM operation. Only one PM unit per superslice so we use the whole
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@ -808,6 +808,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
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setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
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setOperationAction(ISD::FMA, MVT::f128, Legal);
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setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
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setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
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setTruncStoreAction(MVT::f128, MVT::f64, Expand);
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setTruncStoreAction(MVT::f128, MVT::f32, Expand);
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}
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}
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@ -1326,6 +1326,9 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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(outs vssrc:$XT), (ins vssrc:$XB),
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"xsresp $XT, $XB", IIC_VecFP,
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[(set f32:$XT, (PPCfre f32:$XB))]>;
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def XSRSP : XX2Form<60, 281,
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(outs vssrc:$XT), (ins vsfrc:$XB),
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"xsrsp $XT, $XB", IIC_VecFP, []>;
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def XSSQRTSP : XX2Form<60, 11,
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(outs vssrc:$XT), (ins vssrc:$XB),
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"xssqrtsp $XT, $XB", IIC_FPSqrtS,
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@ -2370,6 +2373,17 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
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!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
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// [PO VRT XO VRB XO /]
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class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
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list<dag> pattern>
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: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB),
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!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
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// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
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class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
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list<dag> pattern>
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: X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isDOT;
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let UseVSXReg = 1 in {
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// [PO T XO B XO BX /]
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class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
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@ -2521,8 +2535,8 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
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// Round & Convert QP -> DP (dword[1] is set to zero)
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def XSCVQPDP : X_VT5_XO5_VB5 <63, 20, 836, "xscvqpdp" , []>;
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def XSCVQPDPO : X_VT5_XO5_VB5_Ro<63, 20, 836, "xscvqpdpo", []>;
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def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
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def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", []>;
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// Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
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def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
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@ -3363,7 +3377,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 1),
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(STXSIBX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
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// Round & Convert QP -> DP/SP
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def : Pat<(f64 (fpround f128:$src)), (f64 (XSCVQPDP $src))>;
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def : Pat<(f32 (fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
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} // end HasP9Vector, AddedComplexity
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let Predicates = [HasP9Vector] in {
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let isPseudo = 1 in {
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let mayStore = 1 in {
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@ -398,3 +398,157 @@ entry:
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Convert QP to DP
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@f128Array = global [4 x fp128]
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[fp128 0xL00000000000000004004C00000000000,
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fp128 0xLF000000000000000400808AB851EB851,
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fp128 0xL5000000000000000400E0C26324C8366,
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fp128 0xL8000000000000000400A24E2E147AE14], align 16
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@f128global = global fp128 0xL300000000000000040089CA8F5C28F5C, align 16
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; Function Attrs: norecurse nounwind readonly
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define double @qpConv2dp(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qpConv2dp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv 2, 0(3)
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; CHECK-NEXT: xscvqpdp 2, 2
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; CHECK-NEXT: xxlor 1, 2, 2
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%conv = fptrunc fp128 %0 to double
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ret double %conv
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}
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; Function Attrs: norecurse nounwind
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define void @qpConv2dp_02(double* nocapture %res) {
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; CHECK-LABEL: qpConv2dp_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 4, 2, .LC6@toc@ha
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; CHECK-NEXT: ld 4, .LC6@toc@l(4)
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; CHECK-NEXT: lxvx 2, 0, 4
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; CHECK-NEXT: xscvqpdp 2, 2
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; CHECK-NEXT: stxsd 2, 0(3)
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* @f128global, align 16
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%conv = fptrunc fp128 %0 to double
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store double %conv, double* %res, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
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; CHECK-LABEL: qpConv2dp_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 5, 2, .LC7@toc@ha
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; CHECK-NEXT: sldi 4, 4, 3
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; CHECK-NEXT: ld 5, .LC7@toc@l(5)
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; CHECK-NEXT: lxvx 2, 0, 5
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; CHECK-NEXT: xscvqpdp 2, 2
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; CHECK-NEXT: stxsdx 2, 3, 4
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16
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%conv = fptrunc fp128 %0 to double
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds double, double* %res, i64 %idxprom
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store double %conv, double* %arrayidx, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @qpConv2dp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, double* nocapture %res) {
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; CHECK-LABEL: qpConv2dp_04:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv 2, 0(3)
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; CHECK-NEXT: lxv 3, 0(4)
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; CHECK-NEXT: xsaddqp 2, 2, 3
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; CHECK-NEXT: xscvqpdp 2, 2
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; CHECK-NEXT: stxsd 2, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%add = fadd fp128 %0, %1
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%conv = fptrunc fp128 %add to double
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store double %conv, double* %res, align 8
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ret void
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}
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; Convert QP to SP
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; Function Attrs: norecurse nounwind readonly
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define float @qpConv2sp(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qpConv2sp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv 2, 0(3)
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; CHECK-NEXT: xscvqpdpo 2, 2
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; CHECK-NEXT: xsrsp 1, 2
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%conv = fptrunc fp128 %0 to float
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ret float %conv
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}
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; Function Attrs: norecurse nounwind
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define void @qpConv2sp_02(float* nocapture %res) {
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; CHECK-LABEL: qpConv2sp_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 4, 2, .LC6@toc@ha
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; CHECK-NEXT: ld 4, .LC6@toc@l(4)
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; CHECK-NEXT: lxvx 2, 0, 4
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; CHECK-NEXT: xscvqpdpo 2, 2
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; CHECK-NEXT: xsrsp 0, 2
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; CHECK-NEXT: stfs 0, 0(3)
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* @f128global, align 16
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%conv = fptrunc fp128 %0 to float
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store float %conv, float* %res, align 4
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) {
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; CHECK-LABEL: qpConv2sp_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 5, 2, .LC7@toc@ha
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; CHECK-NEXT: sldi 4, 4, 2
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; CHECK-NEXT: ld 5, .LC7@toc@l(5)
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; CHECK-NEXT: lxv 2, 48(5)
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; CHECK-NEXT: xscvqpdpo 2, 2
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; CHECK-NEXT: xsrsp 0, 2
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; CHECK-NEXT: stfsx 0, 3, 4
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16
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%conv = fptrunc fp128 %0 to float
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds float, float* %res, i64 %idxprom
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store float %conv, float* %arrayidx, align 4
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @qpConv2sp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, float* nocapture %res) {
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; CHECK-LABEL: qpConv2sp_04:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv 2, 0(3)
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; CHECK-NEXT: lxv 3, 0(4)
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; CHECK-NEXT: xsaddqp 2, 2, 3
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; CHECK-NEXT: xscvqpdpo 2, 2
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; CHECK-NEXT: xsrsp 0, 2
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; CHECK-NEXT: stfs 0, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%add = fadd fp128 %0, %1
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%conv = fptrunc fp128 %add to float
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store float %conv, float* %res, align 4
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ret void
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}
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