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[DAGCombiner] Bail out if vector size is not a multiple

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For the included test case, the DAG transformation
  concat_vectors(scalar, undef) -> scalar_to_vector(sclr)
would attempt to create a v2i32 vector for a v9i8
concat_vector.  Bail out to avoid creating a bitcast with
mismatching sizes later on.

Differential Revision: https://reviews.llvm.org/D42379

llvm-svn: 323312
This commit is contained in:
Sven van Haastregt 2018-01-24 09:53:47 +00:00
parent d06cda9f41
commit 46e41bf2fe
2 changed files with 16 additions and 0 deletions
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4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -15188,6 +15188,10 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
return SDValue();
// Bail out if the vector size is not a multiple of the scalar size.
if (VT.getSizeInBits() % SclTy.getSizeInBits())
return SDValue();
unsigned VNTNumElms = VT.getSizeInBits() / SclTy.getSizeInBits();
if (VNTNumElms < 2)
return SDValue();

12
test/CodeGen/AMDGPU/concat_vectors.ll
View File

@ -294,3 +294,15 @@ bb:
store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
ret void
}
; FUNC-LABEL: {{^}}concat_vector_crash2:
; SI: s_endpgm
define amdgpu_kernel void @concat_vector_crash2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) {
%tmp = load i32, i32 addrspace(1)* %in, align 1
%tmp1 = trunc i32 %tmp to i24
%tmp2 = bitcast i24 %tmp1 to <3 x i8>
%tmp3 = shufflevector <3 x i8> %tmp2, <3 x i8> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef>
%tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 7, i8 8>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>
store <8 x i8> %tmp4, <8 x i8> addrspace(1)* %out, align 8
ret void
}