From 46f0e9cf636321ccb26cf423a422fa624b76be80 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Thu, 14 Apr 2016 13:43:17 +0000 Subject: [PATCH] Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301 --- lib/Target/Mips/Mips32r6InstrInfo.td | 5 +- lib/Target/Mips/Mips64r6InstrInfo.td | 3 + .../Mips/compactbranches/compact-branches.ll | 60 +++++++++---------- test/CodeGen/Mips/llvm-ir/call.ll | 22 ++++--- test/CodeGen/Mips/llvm-ir/indirectbr.ll | 2 +- test/CodeGen/Mips/llvm-ir/ret.ll | 8 +-- test/CodeGen/Mips/mips64-f128.ll | 10 ++-- .../Mips/mips32r6/valid-mips32r6-el.txt | 2 + .../Mips/mips32r6/valid-mips32r6.txt | 2 + .../Mips/mips64r6/valid-mips64r6-el.txt | 2 + .../Mips/mips64r6/valid-mips64r6.txt | 2 + test/MC/Mips/mips32r6/valid.s | 2 + test/MC/Mips/mips64r6/valid.s | 2 + 13 files changed, 73 insertions(+), 49 deletions(-) diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 0a5d887e4f9..b6e8dce7454 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -819,8 +819,11 @@ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; } -def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6; +def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32; +def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; + +def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; //===----------------------------------------------------------------------===// // // Patterns and Pseudo Instructions diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index 892231e1fa3..334e25bf85e 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -133,6 +133,9 @@ def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6; def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6; +def : MipsInstAlias<"jrc $rs", (JIC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6; + +def : MipsInstAlias<"jalrc $rs", (JIALC64 GPR64Opnd:$rs, 0), 1>, ISA_MIPS64R6; //===----------------------------------------------------------------------===// // // Patterns and Pseudo Instructions diff --git a/test/CodeGen/Mips/compactbranches/compact-branches.ll b/test/CodeGen/Mips/compactbranches/compact-branches.ll index b489a23f69e..a7e92195ee9 100644 --- a/test/CodeGen/Mips/compactbranches/compact-branches.ll +++ b/test/CodeGen/Mips/compactbranches/compact-branches.ll @@ -4,9 +4,9 @@ ; Function Attrs: nounwind define void @l() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call1 = tail call i32 @j() %cmp = icmp eq i32 %call, %call1 ; CHECK: bnec @@ -15,12 +15,12 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext -2) br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } @@ -33,9 +33,9 @@ declare void @f(i32 signext) ; Function Attrs: define void @l2() { define void @l2() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call1 = tail call i32 @i() %cmp = icmp eq i32 %call, %call1 ; CHECK beqc @@ -44,12 +44,12 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext -1) br label %if.end if.end: ; preds = %entry, %if.then -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } @@ -58,7 +58,7 @@ declare i32 @i() ; Function Attrs: nounwind define void @l3() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() %cmp = icmp slt i32 %call, 0 ; CHECK : bgez @@ -67,12 +67,12 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext 0) br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } @@ -91,16 +91,16 @@ if.then: ; preds = %entry: br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } ; Function Attrs: nounwind define void @l5() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() -; PIC: jialc $25, 0 +; PIC: jalrc $25 %cmp = icmp sgt i32 %call, 0 ; CHECK: blezc br i1 %cmp, label %if.then, label %if.end @@ -108,21 +108,21 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext 2) br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } ; Function Attrs: nounwind define void @l6() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() -; PIC: jialc $25, 0 +; PIC: jalrc $25 %cmp = icmp sgt i32 %call, -1 ; CHECK: bltzc br i1 %cmp, label %if.then, label %if.end @@ -130,19 +130,19 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext 3) br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } ; Function Attrs: nounwind define void @l7() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() %cmp = icmp eq i32 %call, 0 ; CHECK: bnezc @@ -151,19 +151,19 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext 4) br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } ; Function Attrs: nounwind define void @l8() { entry: -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = tail call i32 @k() %cmp = icmp eq i32 %call, 0 ; CHECK: beqzc @@ -172,12 +172,12 @@ entry: if.then: ; preds = %entry: ; STATIC: nop ; STATIC: jal -; PIC: jialc $25, 0 +; PIC: jalrc $25 tail call void @f(i32 signext 5) br label %if.end if.end: ; preds = %entry, %if.then -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret void } @@ -187,20 +187,20 @@ entry: store i8* ()* %i, i8* ()** %i.addr, align 4 ; STATIC32: jal ; STATIC32: nop -; PIC: jialc $25, 0 +; PIC: jalrc $25 %call = call i32 @k() -; PIC: jialc $25, 0 +; PIC: jalrc $25 %cmp = icmp ne i32 %call, 0 ; CHECK: beqzc br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry %0 = load i8* ()*, i8* ()** %i.addr, align 4 -; CHECK: jialc $25, 0 +; CHECK: jalrc $25 %call1 = call i8* %0() br label %if.end if.end: ; preds = %if.then, %entry -; CHECK: jic $ra, 0 +; CHECK: jrc $ra ret i32 -1 } diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index da3ffaf64b1..063b7465aed 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -26,9 +26,10 @@ define i32 @call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) ; NOT-R6C: jalr $[[TGT]] -; R6C: jialc $[[TGT]], 0 +; R6C: jalrc $[[TGT]] call void @extern_void_void() +; R6C: jrc $ra ret i32 0 } @@ -40,10 +41,11 @@ define i32 @call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) ; NOT-R6C: jalr $[[TGT]] -; R6C: jialc $[[TGT]], 0 +; R6C: jalrc $[[TGT]] %1 = call i32 @extern_i32_void() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -58,11 +60,12 @@ define float @call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) ; NOT-R6C: jalr $[[TGT]] -; R6C: jialc $[[TGT]], 0 +; R6C: jalrc $[[TGT]] %1 = call float @extern_float_void() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -110,10 +113,10 @@ define i32 @indirect_call_void_void(void ()* %addr) { ; ALL: move $25, $4 ; NOT-R6C: jalr $25 -; R6C: jialc $25, 0 - +; R6C: jalrc $25 call void %addr() +; R6C: jrc $ra ret i32 0 } @@ -122,11 +125,12 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) { ; ALL: move $25, $4 ; NOT-R6C: jalr $25 -; R6C: jialc $25, 0 +; R6C: jalrc $25 %1 = call i32 %addr() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -135,11 +139,12 @@ define float @indirect_call_float_void(float ()* %addr) { ; ALL: move $25, $4 ; NOT-R6C: jalr $25 -; R6C: jialc $25, 0 +; R6C: jalrc $25 %1 = call float %addr() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -197,10 +202,11 @@ define i32 @jal_only_allows_symbols() { ; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234 ; ALL-NOT: {{jal }} ; NOT-R6C: jalr $[[TGT]] -; R6C: jialc $[[TGT]], 0 +; R6C: jalrc $[[TGT]] ; ALL-NOT: {{jal }} call void () inttoptr (i32 1234 to void ()*)() +; R6C: jrc $ra ret i32 0 } diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll index 4fdce5a0490..26c02edee51 100644 --- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -15,7 +15,7 @@ define i32 @br(i8 *%addr) { ; ALL-LABEL: br: ; NOT-R6: jr $4 #