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Change the x86 32-bit scheduler to register pressure and fix up the

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corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.

llvm-svn: 127441
This commit is contained in:
Eric Christopher 2011-03-11 01:05:58 +00:00
parent d5d2d4a158
commit 46f43c9cce
6 changed files with 11 additions and 6 deletions
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8
lib/Target/X86/X86ISelLowering.cpp
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@ -221,7 +221,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// X86 is weird, it always uses i8 for shift amounts and setcc results. // X86 is weird, it always uses i8 for shift amounts and setcc results.
setBooleanContents(ZeroOrOneBooleanContent); setBooleanContents(ZeroOrOneBooleanContent);
setSchedulingPreference(Sched::ILP);
// For 64-bit since we have so many registers use the ILP scheduler, for
// 32-bit code use the register pressure specific scheduling.
if (Subtarget->is64Bit())
setSchedulingPreference(Sched::ILP);
else
setSchedulingPreference(Sched::RegPressure);
setStackPointerRegisterToSaveRestore(X86StackPtr); setStackPointerRegisterToSaveRestore(X86StackPtr);
if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {

1
test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
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@ -1,4 +1,3 @@
; XFAIL: *
; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& \ ; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& \
; RUN: not grep {Number of register spills} ; RUN: not grep {Number of register spills}
; END. ; END.

2
test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
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@ -1,6 +1,6 @@
; Check that eh_return & unwind_init were properly lowered ; Check that eh_return & unwind_init were properly lowered
; RUN: llc < %s | grep %ebp | count 7 ; RUN: llc < %s | grep %ebp | count 7
; RUN: llc < %s | grep %edx | count 5 ; RUN: llc < %s | grep %ecx | count 5
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i386-pc-linux" target triple = "i386-pc-linux"

3
test/CodeGen/X86/fold-pcmpeqd-0.ll
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@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep pcmpeqd | count 1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI0_2 | count 2
; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
; This testcase shouldn't need to spill the -1 value, ; This testcase shouldn't need to spill the -1 value,

1
test/CodeGen/X86/pr1505b.ll
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@ -1,4 +1,3 @@
; XFAIL: *
; RUN: llc < %s -mcpu=i486 | grep fstpl | count 5 ; RUN: llc < %s -mcpu=i486 | grep fstpl | count 5
; RUN: llc < %s -mcpu=i486 | grep fstps | count 2 ; RUN: llc < %s -mcpu=i486 | grep fstps | count 2
; PR1505 ; PR1505

2
test/CodeGen/X86/v-binop-widen.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s ; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s
; CHECK: divps
; CHECK: divss ; CHECK: divss
; CHECK: divps ; CHECK: divps
; CHECK: divps
%vec = type <9 x float> %vec = type <9 x float>
define %vec @vecdiv( %vec %p1, %vec %p2) define %vec @vecdiv( %vec %p1, %vec %p2)