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[AMDGPU][MC][GFX10][WS32] Corrected decoding of dst operand for v_cmp_*_sdwa opcodes

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See bug 43484: https://bugs.llvm.org/show_bug.cgi?id=43484

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D68349

llvm-svn: 373745
This commit is contained in:
Dmitry Preobrazhensky 2019-10-04 13:04:17 +00:00
parent 43ee7ce963
commit 4723a65db1
2 changed files with 8 additions and 1 deletions
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3
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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@ -1173,7 +1173,8 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
int TTmpIdx = getTTmpIdx(Val); int TTmpIdx = getTTmpIdx(Val);
if (TTmpIdx >= 0) { if (TTmpIdx >= 0) {
return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx); auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
return createSRegOperand(TTmpClsId, TTmpIdx);
} else if (Val > SGPR_MAX) { } else if (Val > SGPR_MAX) {
return IsWave64 ? decodeSpecialReg64(Val) return IsWave64 ? decodeSpecialReg64(Val)
: decodeSpecialReg32(Val); : decodeSpecialReg32(Val);

6
test/MC/Disassembler/AMDGPU/vcmp-gfx10.txt Normal file
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@ -0,0 +1,6 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10,W32 %s
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10,W64 %s
# W32: v_cmp_class_f16_sdwa ttmp14, v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x1e,0x7d,0x01,0xfa,0x06,0x06]
# W64: v_cmp_class_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x1e,0x7d,0x01,0xfa,0x06,0x06]
0xf9,0x04,0x1e,0x7d,0x01,0xfa,0x06,0x06