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[X86][Haswell][SchedModel] Fix WriteMULm latency.

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The latency for the WriteMULm class was set to 4, which is actually lower than the latency for WriteMULr (5). 
A better estimate would be 4 added to WriteMULr, that is, 9.

llvm-svn: 230634
This commit is contained in:
Michael Kuperstein 2015-02-26 14:30:09 +00:00
parent 13407e3fb6
commit 47282b6bbf
1 changed files with 1 additions and 1 deletions
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2
lib/Target/X86/X86SchedHaswell.td
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@ -1895,7 +1895,7 @@ def : InstRW<[WriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>;
// x,m / v,v,m.
def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> {
let Latency = 4;
let Latency = 9;
let NumMicroOps = 2;
let ResourceCycles = [1, 1];
}