1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00

Fix ScalarEvolution's Xor handling to not assume that an And

that gets recognized with a SCEVZeroExtendExpr must be an And
with a low-bits mask. With r73540, this is no longer the case.

llvm-svn: 73594
This commit is contained in:
Dan Gohman 2009-06-17 01:22:39 +00:00
parent db78831eaa
commit 473789f75a
2 changed files with 17 additions and 3 deletions

View File

@ -2453,9 +2453,12 @@ SCEVHandle ScalarEvolution::createSCEV(Value *V) {
if (BO->getOpcode() == Instruction::And &&
LCI->getValue() == CI->getValue())
if (const SCEVZeroExtendExpr *Z =
dyn_cast<SCEVZeroExtendExpr>(getSCEV(U->getOperand(0))))
return getZeroExtendExpr(getNotSCEV(Z->getOperand()),
U->getType());
dyn_cast<SCEVZeroExtendExpr>(getSCEV(U->getOperand(0)))) {
SCEVHandle ZO = Z->getOperand();
if (APIntOps::isMask(getTypeSizeInBits(ZO->getType()),
CI->getValue()))
return getZeroExtendExpr(getNotSCEV(ZO), U->getType());
}
}
break;

View File

@ -0,0 +1,11 @@
; RUN: llvm-as < %s | opt -scalar-evolution -disable-output -analyze | grep {\\--> %z}
; ScalarEvolution shouldn't try to analyze %s into something like
; --> (zext i4 (-1 + (-1 * (trunc i64 (8 * %x) to i4))) to i64)
define i64 @foo(i64 %x) {
%a = shl i64 %x, 3
%t = and i64 %a, 8
%z = xor i64 %t, 8
ret i64 %z
}