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[X86][Btver2] Merge equivalent VBLENDVY + VPERMILY schedule groups

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Thanks to Craig Topper for noticing this.

llvm-svn: 327789
This commit is contained in:
Simon Pilgrim 2018-03-18 10:22:35 +00:00
parent 9b5349a92b
commit 476b586d94
1 changed files with 2 additions and 14 deletions
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16
lib/Target/X86/X86ScheduleBtVer2.td
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@ -650,14 +650,14 @@ def JWriteVPERMY: SchedWriteRes<[JFPU01]> {
let ResourceCycles = [6];
let NumMicroOps = 6;
}
def : InstRW<[JWriteVPERMY], (instrs VPERMILPDYrr, VPERMILPSYrr)>;
def : InstRW<[JWriteVPERMY], (instrs VBLENDVPDYrr, VBLENDVPSYrr, VPERMILPDYrr, VPERMILPSYrr)>;
def JWriteVPERMYLd: SchedWriteRes<[JLAGU, JFPU01]> {
let Latency = 8;
let ResourceCycles = [1, 6];
let NumMicroOps = 6;
}
def : InstRW<[JWriteVPERMYLd, ReadAfterLd], (instrs VPERMILPDYrm, VPERMILPSYrm)>;
def : InstRW<[JWriteVPERMYLd, ReadAfterLd], (instrs VBLENDVPDYrm, VBLENDVPSYrm, VPERMILPDYrm, VPERMILPSYrm)>;
def JWriteShuffleY: SchedWriteRes<[JFPU01]> {
let ResourceCycles = [2];
@ -674,18 +674,6 @@ def JWriteShuffleYLd: SchedWriteRes<[JLAGU, JFPU01]> {
def : InstRW<[JWriteShuffleYLd, ReadAfterLd], (instrs VMOVDDUPYrm, VMOVSHDUPYrm, VMOVSLDUPYrm,
VPERMILPDYmi, VPERMILPSYmi, VSHUFPDYrmi, VSHUFPSYrmi)>;
def JWriteVBlendVPY: SchedWriteRes<[JFPU01]> {
let Latency = 3;
let ResourceCycles = [6];
}
def : InstRW<[JWriteVBlendVPY], (instrs VBLENDVPDYrr, VBLENDVPSYrr, VPERMILPDYrr, VPERMILPSYrr)>;
def JWriteVBlendVPYLd: SchedWriteRes<[JLAGU, JFPU01]> {
let Latency = 8;
let ResourceCycles = [1, 6];
}
def : InstRW<[JWriteVBlendVPYLd, ReadAfterLd], (instrs VBLENDVPDYrm, VBLENDVPSYrm)>;
def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01]> {
let Latency = 6;
let ResourceCycles = [1, 4];