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[x86] add smin/smax with zero tests

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These are vector tests corresponding to the discussion at:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/106868.html

Apart from the lack of min/max matching, the and/andn difference 
shows a lack of DAG-level canonicalization.

llvm-svn: 286737
This commit is contained in:
Sanjay Patel 2016-11-13 00:32:39 +00:00
parent c212604eb9
commit 479c8dead8
1 changed files with 64 additions and 0 deletions
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64
test/CodeGen/X86/vec_minmax_match.ll
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@ -32,6 +32,38 @@ define <4 x i32> @smin_vec2(<4 x i32> %x) {
ret <4 x i32> %sel
}
; Z = X -nsw Y
; (X >s Y) ? 0 : Z ==> (Z >s 0) ? 0 : Z ==> SMIN(Z, 0)
define <4 x i32> @smin_vec3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: smin_vec3:
; CHECK: # BB#0:
; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2
; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpandn %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq
;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp sgt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
ret <4 x i32> %sel
}
; Z = X -nsw Y
; (X <s Y) ? Z : 0 ==> (Z <s 0) ? Z : 0 ==> SMIN(Z, 0)
define <4 x i32> @smin_vec4(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: smin_vec4:
; CHECK: # BB#0:
; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2
; CHECK-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq
;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp slt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer
ret <4 x i32> %sel
}
define <4 x i32> @smax_vec1(<4 x i32> %x) {
; CHECK-LABEL: smax_vec1:
; CHECK: # BB#0:
@ -60,6 +92,38 @@ define <4 x i32> @smax_vec2(<4 x i32> %x) {
ret <4 x i32> %sel
}
; Z = X -nsw Y
; (X <s Y) ? 0 : Z ==> (Z <s 0) ? 0 : Z ==> SMAX(Z, 0)
define <4 x i32> @smax_vec3(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: smax_vec3:
; CHECK: # BB#0:
; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2
; CHECK-NEXT: vpcmpgtd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vpandn %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq
;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp slt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
ret <4 x i32> %sel
}
; Z = X -nsw Y
; (X >s Y) ? Z : 0 ==> (Z >s 0) ? Z : 0 ==> SMAX(Z, 0)
define <4 x i32> @smax_vec4(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: smax_vec4:
; CHECK: # BB#0:
; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2
; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0
; CHECK-NEXT: retq
;
%sub = sub nsw <4 x i32> %x, %y
%cmp = icmp sgt <4 x i32> %x, %y
%sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer
ret <4 x i32> %sel
}
define <4 x i32> @umax_vec1(<4 x i32> %x) {
; CHECK-LABEL: umax_vec1:
; CHECK: # BB#0: