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Implement aarch64 neon instruction class SIMD misc.
llvm-svn: 194656
This commit is contained in:
Kevin Qin
parent
5701cc8c01
commit
47a3b639e3
@ -22,6 +22,39 @@ def int_aarch64_neon_vacgeq :
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def int_aarch64_neon_vacgtq :
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Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
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// Vector saturating accumulate
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def int_aarch64_neon_suqadd : Neon_2Arg_Intrinsic;
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def int_aarch64_neon_usqadd : Neon_2Arg_Intrinsic;
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// Vector Bitwise reverse
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def int_aarch64_neon_rbit : Neon_1Arg_Intrinsic;
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// Vector extract and narrow
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def int_aarch64_neon_xtn :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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// Vector floating-point convert
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def int_aarch64_neon_frintn : Neon_1Arg_Intrinsic;
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def int_aarch64_neon_fsqrt : Neon_1Arg_Intrinsic;
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def int_aarch64_neon_fcvtxn :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtns :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtnu :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtps :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtpu :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtms :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtmu :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtas :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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def int_aarch64_neon_fcvtau :
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Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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// Vector maxNum (Floating Point)
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def int_aarch64_neon_vmaxnm : Neon_2Arg_Intrinsic;
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@ -338,6 +338,30 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
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setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
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setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
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setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
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setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
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setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
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setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
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setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
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setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
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setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
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setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
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setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
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setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
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}
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}
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@ -891,6 +915,12 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "AArch64ISD::NEON_VDUP";
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case AArch64ISD::NEON_VDUPLANE:
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return "AArch64ISD::NEON_VDUPLANE";
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case AArch64ISD::NEON_REV16:
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return "AArch64ISD::NEON_REV16";
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case AArch64ISD::NEON_REV32:
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return "AArch64ISD::NEON_REV32";
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case AArch64ISD::NEON_REV64:
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return "AArch64ISD::NEON_REV64";
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case AArch64ISD::NEON_LD1_UPD:
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return "AArch64ISD::NEON_LD1_UPD";
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case AArch64ISD::NEON_LD2_UPD:
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@ -3797,6 +3827,36 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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return SDValue();
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}
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/// isREVMask - Check if a vector shuffle corresponds to a REV
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/// instruction with the specified blocksize. (The order of the elements
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/// within each block of the vector is reversed.)
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static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
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assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
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"Only possible block sizes for REV are: 16, 32, 64");
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unsigned EltSz = VT.getVectorElementType().getSizeInBits();
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if (EltSz == 64)
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return false;
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unsigned NumElts = VT.getVectorNumElements();
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unsigned BlockElts = M[0] + 1;
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// If the first shuffle index is UNDEF, be optimistic.
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if (M[0] < 0)
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BlockElts = BlockSize / EltSz;
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if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
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return false;
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for (unsigned i = 0; i < NumElts; ++i) {
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if (M[i] < 0)
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continue; // ignore UNDEF indices
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if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
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return false;
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}
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return true;
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}
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SDValue
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AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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SelectionDAG &DAG) const {
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@ -3816,6 +3876,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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if (EltSize > 64)
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return SDValue();
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if (isREVMask(ShuffleMask, VT, 64))
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return DAG.getNode(AArch64ISD::NEON_REV64, dl, VT, V1);
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if (isREVMask(ShuffleMask, VT, 32))
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return DAG.getNode(AArch64ISD::NEON_REV32, dl, VT, V1);
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if (isREVMask(ShuffleMask, VT, 16))
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return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1);
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// If the element of shuffle mask are all the same constant, we can
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// transform it into either NEON_VDUP or NEON_VDUPLANE
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if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
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@ -125,6 +125,11 @@ namespace AArch64ISD {
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// Vector FP move immediate
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NEON_FMOVIMM,
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// Vector Element reverse
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NEON_REV64,
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NEON_REV32,
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NEON_REV16,
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// Vector compare
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NEON_CMP,
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@ -46,6 +46,10 @@ def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
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def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
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def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
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def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
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def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
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def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
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def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
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def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
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[SDTCisVec<0>]>>;
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def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
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@ -1610,6 +1614,21 @@ def Neon_low4f : PatFrag<(ops node:$in),
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(v2f32 (extract_subvector (v4f32 node:$in),
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(iPTR 0)))>;
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def neon_uimm3_shift : Operand<i32>,
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ImmLeaf<i32, [{return Imm < 8;}]> {
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let ParserMatchClass = uimm3_asmoperand;
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}
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def neon_uimm4_shift : Operand<i32>,
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ImmLeaf<i32, [{return Imm < 16;}]> {
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let ParserMatchClass = uimm4_asmoperand;
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}
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def neon_uimm5_shift : Operand<i32>,
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ImmLeaf<i32, [{return Imm < 32;}]> {
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let ParserMatchClass = uimm5_asmoperand;
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}
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class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
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string SrcT, ValueType DestTy, ValueType SrcTy,
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Operand ImmTy, SDPatternOperator ExtOp>
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@ -1619,7 +1638,7 @@ class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
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[(set (DestTy VPR128:$Rd),
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(DestTy (shl
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(DestTy (ExtOp (SrcTy VPR64:$Rn))),
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(DestTy (Neon_vdup (i32 imm:$Imm))))))],
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(DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
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NoItinerary>;
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class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
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@ -1633,40 +1652,40 @@ class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
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(DestTy (shl
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(DestTy (ExtOp
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(SrcTy (getTop VPR128:$Rn)))),
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(DestTy (Neon_vdup (i32 imm:$Imm))))))],
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(DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
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NoItinerary>;
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multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
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SDNode ExtOp> {
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// 64-bit vector types.
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def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
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uimm3, ExtOp> {
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neon_uimm3_shift, ExtOp> {
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let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
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}
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def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
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uimm4, ExtOp> {
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neon_uimm4_shift, ExtOp> {
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let Inst{22-20} = 0b001; // immh:immb = 001xxxx
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}
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def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
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uimm5, ExtOp> {
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neon_uimm5_shift, ExtOp> {
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let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
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}
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// 128-bit vector types
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def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b",
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v8i16, v8i8, 8, uimm3, ExtOp, Neon_High16B> {
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def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
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8, neon_uimm3_shift, ExtOp, Neon_High16B> {
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let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
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}
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def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h",
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v4i32, v4i16, 4, uimm4, ExtOp, Neon_High8H> {
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def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
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4, neon_uimm4_shift, ExtOp, Neon_High8H> {
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let Inst{22-20} = 0b001; // immh:immb = 001xxxx
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}
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def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s",
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v2i64, v2i32, 2, uimm5, ExtOp, Neon_High4S> {
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def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
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2, neon_uimm5_shift, ExtOp, Neon_High4S> {
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let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
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}
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@ -4693,25 +4712,25 @@ def neon_uimm0_bare : Operand<i64>,
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}
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def neon_uimm1_bare : Operand<i64>,
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ImmLeaf<i64, [{(void)Imm; return true;}]> {
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ImmLeaf<i64, [{return Imm < 2;}]> {
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let ParserMatchClass = neon_uimm1_asmoperand;
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let PrintMethod = "printUImmBareOperand";
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}
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def neon_uimm2_bare : Operand<i64>,
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ImmLeaf<i64, [{(void)Imm; return true;}]> {
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ImmLeaf<i64, [{return Imm < 4;}]> {
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let ParserMatchClass = neon_uimm2_asmoperand;
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let PrintMethod = "printUImmBareOperand";
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}
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def neon_uimm3_bare : Operand<i64>,
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ImmLeaf<i64, [{(void)Imm; return true;}]> {
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ImmLeaf<i64, [{return Imm < 8;}]> {
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let ParserMatchClass = uimm3_asmoperand;
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let PrintMethod = "printUImmBareOperand";
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}
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def neon_uimm4_bare : Operand<i64>,
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ImmLeaf<i64, [{(void)Imm; return true;}]> {
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ImmLeaf<i64, [{return Imm < 16;}]> {
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let ParserMatchClass = uimm4_asmoperand;
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let PrintMethod = "printUImmBareOperand";
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}
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@ -5096,13 +5115,13 @@ def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
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def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
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def neon_uimm3 : Operand<i64>,
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ImmLeaf<i64, [{(void)Imm; return true;}]> {
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ImmLeaf<i64, [{return Imm < 8;}]> {
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let ParserMatchClass = uimm3_asmoperand;
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let PrintMethod = "printUImmHexOperand";
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}
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def neon_uimm4 : Operand<i64>,
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ImmLeaf<i64, [{(void)Imm; return true;}]> {
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ImmLeaf<i64, [{return Imm < 16;}]> {
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let ParserMatchClass = uimm4_asmoperand;
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let PrintMethod = "printUImmHexOperand";
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}
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@ -6538,6 +6557,855 @@ def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
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def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
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(v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
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class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
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bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
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SDPatternOperator Neon_Rev>
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: NeonI_2VMisc<Q, U, size, opcode,
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(outs ResVPR:$Rd), (ins ResVPR:$Rn),
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asmop # "\t$Rd." # Res # ", $Rn." # Res,
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[(set (ResTy ResVPR:$Rd),
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(ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
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NoItinerary> ;
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def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
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v16i8, Neon_rev64>;
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def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
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v8i16, Neon_rev64>;
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def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
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v4i32, Neon_rev64>;
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def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
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v8i8, Neon_rev64>;
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def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
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v4i16, Neon_rev64>;
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def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
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v2i32, Neon_rev64>;
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def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
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def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
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def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
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v16i8, Neon_rev32>;
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def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
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v8i16, Neon_rev32>;
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def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
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v8i8, Neon_rev32>;
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def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
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v4i16, Neon_rev32>;
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def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
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v16i8, Neon_rev16>;
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def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
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v8i8, Neon_rev16>;
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multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
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SDPatternOperator Neon_Padd> {
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def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.8h, $Rn.16b",
|
||||
[(set (v8i16 VPR128:$Rd),
|
||||
(v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.8b",
|
||||
[(set (v4i16 VPR64:$Rd),
|
||||
(v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.8h",
|
||||
[(set (v4i32 VPR128:$Rd),
|
||||
(v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.4h",
|
||||
[(set (v2i32 VPR64:$Rd),
|
||||
(v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.4s",
|
||||
[(set (v2i64 VPR128:$Rd),
|
||||
(v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.1d, $Rn.2s",
|
||||
[(set (v1i64 VPR64:$Rd),
|
||||
(v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
}
|
||||
|
||||
defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
|
||||
int_arm_neon_vpaddls>;
|
||||
defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
|
||||
int_arm_neon_vpaddlu>;
|
||||
|
||||
multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
|
||||
SDPatternOperator Neon_Padd> {
|
||||
let Constraints = "$src = $Rd" in {
|
||||
def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.8h, $Rn.16b",
|
||||
[(set (v8i16 VPR128:$Rd),
|
||||
(v8i16 (Neon_Padd
|
||||
(v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.8b",
|
||||
[(set (v4i16 VPR64:$Rd),
|
||||
(v4i16 (Neon_Padd
|
||||
(v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.8h",
|
||||
[(set (v4i32 VPR128:$Rd),
|
||||
(v4i32 (Neon_Padd
|
||||
(v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.4h",
|
||||
[(set (v2i32 VPR64:$Rd),
|
||||
(v2i32 (Neon_Padd
|
||||
(v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.4s",
|
||||
[(set (v2i64 VPR128:$Rd),
|
||||
(v2i64 (Neon_Padd
|
||||
(v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
|
||||
asmop # "\t$Rd.1d, $Rn.2s",
|
||||
[(set (v1i64 VPR64:$Rd),
|
||||
(v1i64 (Neon_Padd
|
||||
(v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
}
|
||||
}
|
||||
|
||||
defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
|
||||
int_arm_neon_vpadals>;
|
||||
defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
|
||||
int_arm_neon_vpadalu>;
|
||||
|
||||
multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
|
||||
def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.16b, $Rn.16b",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.8h, $Rn.8h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.8b, $Rn.8b",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.4h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2s",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
|
||||
defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
|
||||
defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
|
||||
defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
|
||||
defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
|
||||
|
||||
multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
|
||||
SDPatternOperator Neon_Op> {
|
||||
def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
|
||||
(v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
|
||||
(v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
|
||||
(v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
|
||||
(v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
|
||||
(v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
|
||||
|
||||
def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
|
||||
(v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
|
||||
|
||||
def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
|
||||
(v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
|
||||
}
|
||||
|
||||
defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
|
||||
defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
|
||||
defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
|
||||
|
||||
def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
|
||||
def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
|
||||
|
||||
def : Pat<(v16i8 (sub
|
||||
(v16i8 Neon_AllZero),
|
||||
(v16i8 VPR128:$Rn))),
|
||||
(v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
|
||||
def : Pat<(v8i8 (sub
|
||||
(v8i8 Neon_AllZero),
|
||||
(v8i8 VPR64:$Rn))),
|
||||
(v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
|
||||
def : Pat<(v8i16 (sub
|
||||
(v8i16 (bitconvert (v16i8 Neon_AllZero))),
|
||||
(v8i16 VPR128:$Rn))),
|
||||
(v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
|
||||
def : Pat<(v4i16 (sub
|
||||
(v4i16 (bitconvert (v8i8 Neon_AllZero))),
|
||||
(v4i16 VPR64:$Rn))),
|
||||
(v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
|
||||
def : Pat<(v4i32 (sub
|
||||
(v4i32 (bitconvert (v16i8 Neon_AllZero))),
|
||||
(v4i32 VPR128:$Rn))),
|
||||
(v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
|
||||
def : Pat<(v2i32 (sub
|
||||
(v2i32 (bitconvert (v8i8 Neon_AllZero))),
|
||||
(v2i32 VPR64:$Rn))),
|
||||
(v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
|
||||
def : Pat<(v2i64 (sub
|
||||
(v2i64 (bitconvert (v16i8 Neon_AllZero))),
|
||||
(v2i64 VPR128:$Rn))),
|
||||
(v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
|
||||
|
||||
multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
|
||||
let Constraints = "$src = $Rd" in {
|
||||
def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.16b, $Rn.16b",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.8h, $Rn.8h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
|
||||
asmop # "\t$Rd.8b, $Rn.8b",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.4h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2s",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
}
|
||||
|
||||
defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
|
||||
defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
|
||||
|
||||
multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
|
||||
SDPatternOperator Neon_Op> {
|
||||
def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
|
||||
(v16i8 (!cast<Instruction>(Prefix # 16b)
|
||||
(v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
|
||||
(v8i16 (!cast<Instruction>(Prefix # 8h)
|
||||
(v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
|
||||
(v4i32 (!cast<Instruction>(Prefix # 4s)
|
||||
(v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
|
||||
(v2i64 (!cast<Instruction>(Prefix # 2d)
|
||||
(v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
|
||||
(v8i8 (!cast<Instruction>(Prefix # 8b)
|
||||
(v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
|
||||
|
||||
def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
|
||||
(v4i16 (!cast<Instruction>(Prefix # 4h)
|
||||
(v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
|
||||
|
||||
def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
|
||||
(v2i32 (!cast<Instruction>(Prefix # 2s)
|
||||
(v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
|
||||
}
|
||||
|
||||
defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
|
||||
defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
|
||||
|
||||
multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
|
||||
SDPatternOperator Neon_Op> {
|
||||
def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.16b, $Rn.16b",
|
||||
[(set (v16i8 VPR128:$Rd),
|
||||
(v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.8h, $Rn.8h",
|
||||
[(set (v8i16 VPR128:$Rd),
|
||||
(v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4s",
|
||||
[(set (v4i32 VPR128:$Rd),
|
||||
(v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.8b, $Rn.8b",
|
||||
[(set (v8i8 VPR64:$Rd),
|
||||
(v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.4h",
|
||||
[(set (v4i16 VPR64:$Rd),
|
||||
(v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2s",
|
||||
[(set (v2i32 VPR64:$Rd),
|
||||
(v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
}
|
||||
|
||||
defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
|
||||
defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
|
||||
|
||||
multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
|
||||
bits<5> Opcode> {
|
||||
def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.16b, $Rn.16b",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.8b, $Rn.8b",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
|
||||
defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
|
||||
defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
|
||||
defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
|
||||
|
||||
def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
|
||||
(NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
|
||||
def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
|
||||
(NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
|
||||
|
||||
def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
|
||||
(v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
|
||||
def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
|
||||
(v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
|
||||
|
||||
def : Pat<(v16i8 (xor
|
||||
(v16i8 VPR128:$Rn),
|
||||
(v16i8 Neon_AllOne))),
|
||||
(v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
|
||||
def : Pat<(v8i8 (xor
|
||||
(v8i8 VPR64:$Rn),
|
||||
(v8i8 Neon_AllOne))),
|
||||
(v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
|
||||
def : Pat<(v8i16 (xor
|
||||
(v8i16 VPR128:$Rn),
|
||||
(v8i16 (bitconvert (v16i8 Neon_AllOne))))),
|
||||
(NOT16b VPR128:$Rn)>;
|
||||
def : Pat<(v4i16 (xor
|
||||
(v4i16 VPR64:$Rn),
|
||||
(v4i16 (bitconvert (v8i8 Neon_AllOne))))),
|
||||
(NOT8b VPR64:$Rn)>;
|
||||
def : Pat<(v4i32 (xor
|
||||
(v4i32 VPR128:$Rn),
|
||||
(v4i32 (bitconvert (v16i8 Neon_AllOne))))),
|
||||
(NOT16b VPR128:$Rn)>;
|
||||
def : Pat<(v2i32 (xor
|
||||
(v2i32 VPR64:$Rn),
|
||||
(v2i32 (bitconvert (v8i8 Neon_AllOne))))),
|
||||
(NOT8b VPR64:$Rn)>;
|
||||
def : Pat<(v2i64 (xor
|
||||
(v2i64 VPR128:$Rn),
|
||||
(v2i64 (bitconvert (v16i8 Neon_AllOne))))),
|
||||
(NOT16b VPR128:$Rn)>;
|
||||
|
||||
def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
|
||||
(v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
|
||||
def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
|
||||
(v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
|
||||
|
||||
multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
|
||||
SDPatternOperator Neon_Op> {
|
||||
def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4s",
|
||||
[(set (v4f32 VPR128:$Rd),
|
||||
(v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.2d",
|
||||
[(set (v2f64 VPR128:$Rd),
|
||||
(v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2s",
|
||||
[(set (v2f32 VPR64:$Rd),
|
||||
(v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
}
|
||||
|
||||
defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
|
||||
defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
|
||||
|
||||
multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
|
||||
def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.8b, $Rn.8h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
|
||||
let Constraints = "$Rd = $src" in {
|
||||
def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "2\t$Rd.16b, $Rn.8h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "2\t$Rd.8h, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "2\t$Rd.4s, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
}
|
||||
|
||||
defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
|
||||
defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
|
||||
defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
|
||||
defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
|
||||
|
||||
multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
|
||||
SDPatternOperator Neon_Op> {
|
||||
def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
|
||||
(v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
|
||||
(v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
|
||||
(v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
|
||||
|
||||
def : Pat<(v16i8 (concat_vectors
|
||||
(v8i8 VPR64:$src),
|
||||
(v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(Prefix # 8h16b)
|
||||
(SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
|
||||
VPR128:$Rn)>;
|
||||
|
||||
def : Pat<(v8i16 (concat_vectors
|
||||
(v4i16 VPR64:$src),
|
||||
(v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(Prefix # 4s8h)
|
||||
(SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
|
||||
VPR128:$Rn)>;
|
||||
|
||||
def : Pat<(v4i32 (concat_vectors
|
||||
(v2i32 VPR64:$src),
|
||||
(v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(Prefix # 2d4s)
|
||||
(SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
|
||||
VPR128:$Rn)>;
|
||||
}
|
||||
|
||||
defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
|
||||
defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
|
||||
defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
|
||||
defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
|
||||
|
||||
multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
|
||||
def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd),
|
||||
(ins VPR64:$Rn, uimm_exact8:$Imm),
|
||||
asmop # "\t$Rd.8h, $Rn.8b, $Imm",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd),
|
||||
(ins VPR64:$Rn, uimm_exact16:$Imm),
|
||||
asmop # "\t$Rd.4s, $Rn.4h, $Imm",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd),
|
||||
(ins VPR64:$Rn, uimm_exact32:$Imm),
|
||||
asmop # "\t$Rd.2d, $Rn.2s, $Imm",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd),
|
||||
(ins VPR128:$Rn, uimm_exact8:$Imm),
|
||||
asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd),
|
||||
(ins VPR128:$Rn, uimm_exact16:$Imm),
|
||||
asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
|
||||
(outs VPR128:$Rd),
|
||||
(ins VPR128:$Rn, uimm_exact32:$Imm),
|
||||
asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
|
||||
defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
|
||||
|
||||
class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
|
||||
SDPatternOperator ExtOp, Operand Neon_Imm,
|
||||
string suffix>
|
||||
: Pat<(DesTy (shl
|
||||
(DesTy (ExtOp (OpTy VPR64:$Rn))),
|
||||
(DesTy (Neon_vdup
|
||||
(i32 Neon_Imm:$Imm))))),
|
||||
(!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
|
||||
|
||||
class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
|
||||
SDPatternOperator ExtOp, Operand Neon_Imm,
|
||||
string suffix, PatFrag GetHigh>
|
||||
: Pat<(DesTy (shl
|
||||
(DesTy (ExtOp
|
||||
(OpTy (GetHigh VPR128:$Rn)))),
|
||||
(DesTy (Neon_vdup
|
||||
(i32 Neon_Imm:$Imm))))),
|
||||
(!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
|
||||
|
||||
def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
|
||||
def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
|
||||
def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
|
||||
def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
|
||||
def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
|
||||
def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
|
||||
def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
|
||||
Neon_High16B>;
|
||||
def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
|
||||
Neon_High16B>;
|
||||
def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
|
||||
Neon_High8H>;
|
||||
def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
|
||||
Neon_High8H>;
|
||||
def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
|
||||
Neon_High4S>;
|
||||
def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
|
||||
Neon_High4S>;
|
||||
|
||||
multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
|
||||
def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4h, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
|
||||
let Constraints = "$src = $Rd" in {
|
||||
def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "2\t$Rd.8h, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "2\t$Rd.4s, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
}
|
||||
|
||||
defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
|
||||
|
||||
multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
|
||||
SDPatternOperator f32_to_f16_Op,
|
||||
SDPatternOperator f64_to_f32_Op> {
|
||||
|
||||
def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
|
||||
(!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
|
||||
|
||||
def : Pat<(v8i16 (concat_vectors
|
||||
(v4i16 VPR64:$src),
|
||||
(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(prefix # "4s8h")
|
||||
(v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
|
||||
(v4f32 VPR128:$Rn))>;
|
||||
|
||||
def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
|
||||
(!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
|
||||
|
||||
def : Pat<(v4f32 (concat_vectors
|
||||
(v2f32 VPR64:$src),
|
||||
(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(prefix # "2d4s")
|
||||
(v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
|
||||
(v2f64 VPR128:$Rn))>;
|
||||
}
|
||||
|
||||
defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
|
||||
|
||||
multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
|
||||
bits<5> opcode> {
|
||||
def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2d",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
|
||||
asmop # "2\t$Rd.4s, $Rn.2d",
|
||||
[], NoItinerary> {
|
||||
let Constraints = "$src = $Rd";
|
||||
}
|
||||
|
||||
def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
|
||||
(!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
|
||||
|
||||
def : Pat<(v4f32 (concat_vectors
|
||||
(v2f32 VPR64:$src),
|
||||
(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(prefix # "2d4s")
|
||||
(v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
|
||||
VPR128:$Rn)>;
|
||||
}
|
||||
|
||||
defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
|
||||
|
||||
def Neon_High4Float : PatFrag<(ops node:$in),
|
||||
(extract_subvector (v4f32 node:$in), (iPTR 2))>;
|
||||
|
||||
multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
|
||||
def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.2s",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "2\t$Rd.4s, $Rn.8h",
|
||||
[], NoItinerary>;
|
||||
|
||||
def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "2\t$Rd.2d, $Rn.4s",
|
||||
[], NoItinerary>;
|
||||
}
|
||||
|
||||
defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
|
||||
|
||||
multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
|
||||
def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
|
||||
(!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
|
||||
|
||||
def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
|
||||
(v4i16 (Neon_High8H
|
||||
(v8i16 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
|
||||
|
||||
def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
|
||||
(!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
|
||||
|
||||
def : Pat<(v2f64 (fextend
|
||||
(v2f32 (Neon_High4Float
|
||||
(v4f32 VPR128:$Rn))))),
|
||||
(!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
|
||||
}
|
||||
|
||||
defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
|
||||
|
||||
multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
|
||||
ValueType ResTy4s, ValueType OpTy4s,
|
||||
ValueType ResTy2d, ValueType OpTy2d,
|
||||
ValueType ResTy2s, ValueType OpTy2s,
|
||||
SDPatternOperator Neon_Op> {
|
||||
|
||||
def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4s",
|
||||
[(set (ResTy4s VPR128:$Rd),
|
||||
(ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.2d, $Rn.2d",
|
||||
[(set (ResTy2d VPR128:$Rd),
|
||||
(ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2s",
|
||||
[(set (ResTy2s VPR64:$Rd),
|
||||
(ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
}
|
||||
|
||||
multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
|
||||
bits<5> opcode, SDPatternOperator Neon_Op> {
|
||||
defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
|
||||
v2f64, v2i32, v2f32, Neon_Op>;
|
||||
}
|
||||
|
||||
defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
|
||||
int_aarch64_neon_fcvtns>;
|
||||
defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
|
||||
int_aarch64_neon_fcvtnu>;
|
||||
defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
|
||||
int_aarch64_neon_fcvtps>;
|
||||
defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
|
||||
int_aarch64_neon_fcvtpu>;
|
||||
defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
|
||||
int_aarch64_neon_fcvtms>;
|
||||
defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
|
||||
int_aarch64_neon_fcvtmu>;
|
||||
defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
|
||||
defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
|
||||
defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
|
||||
int_aarch64_neon_fcvtas>;
|
||||
defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
|
||||
int_aarch64_neon_fcvtau>;
|
||||
|
||||
multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
|
||||
bits<5> opcode, SDPatternOperator Neon_Op> {
|
||||
defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
|
||||
v2i64, v2f32, v2i32, Neon_Op>;
|
||||
}
|
||||
|
||||
defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
|
||||
defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
|
||||
|
||||
multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
|
||||
bits<5> opcode, SDPatternOperator Neon_Op> {
|
||||
defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
|
||||
v2f64, v2f32, v2f32, Neon_Op>;
|
||||
}
|
||||
|
||||
defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
|
||||
int_aarch64_neon_frintn>;
|
||||
defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
|
||||
defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
|
||||
defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
|
||||
defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
|
||||
defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
|
||||
defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
|
||||
defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
|
||||
int_arm_neon_vrecpe>;
|
||||
defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
|
||||
int_arm_neon_vrsqrte>;
|
||||
defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111,
|
||||
int_aarch64_neon_fsqrt>;
|
||||
|
||||
multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
|
||||
bits<5> opcode, SDPatternOperator Neon_Op> {
|
||||
def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
|
||||
(outs VPR128:$Rd), (ins VPR128:$Rn),
|
||||
asmop # "\t$Rd.4s, $Rn.4s",
|
||||
[(set (v4i32 VPR128:$Rd),
|
||||
(v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
|
||||
NoItinerary>;
|
||||
|
||||
def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
|
||||
(outs VPR64:$Rd), (ins VPR64:$Rn),
|
||||
asmop # "\t$Rd.2s, $Rn.2s",
|
||||
[(set (v2i32 VPR64:$Rd),
|
||||
(v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
|
||||
NoItinerary>;
|
||||
}
|
||||
|
||||
defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
|
||||
int_arm_neon_vrecpe>;
|
||||
defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
|
||||
int_arm_neon_vrsqrte>;
|
||||
|
||||
// Crypto Class
|
||||
class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
|
||||
string asmop, SDPatternOperator opnode>
|
||||
|
||||
@ -51,8 +51,7 @@ define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
|
||||
|
||||
define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = icmp ne <8 x i8> %A, %B;
|
||||
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
|
||||
ret <8 x i8> %tmp4
|
||||
@ -60,8 +59,7 @@ define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
|
||||
|
||||
define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <16 x i8> %A, %B;
|
||||
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
|
||||
ret <16 x i8> %tmp4
|
||||
@ -69,8 +67,7 @@ define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
|
||||
|
||||
define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = icmp ne <4 x i16> %A, %B;
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
|
||||
ret <4 x i16> %tmp4
|
||||
@ -78,8 +75,7 @@ define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
|
||||
|
||||
define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <8 x i16> %A, %B;
|
||||
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
|
||||
ret <8 x i16> %tmp4
|
||||
@ -87,8 +83,7 @@ define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
|
||||
|
||||
define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = icmp ne <2 x i32> %A, %B;
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -96,8 +91,7 @@ define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
|
||||
|
||||
define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <4 x i32> %A, %B;
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -105,8 +99,7 @@ define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
|
||||
|
||||
define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <2 x i64> %A, %B;
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -867,8 +860,7 @@ define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
|
||||
|
||||
define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
|
||||
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
|
||||
ret <8 x i8> %tmp4
|
||||
@ -876,8 +868,7 @@ define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
|
||||
|
||||
define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
|
||||
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
|
||||
ret <16 x i8> %tmp4
|
||||
@ -885,8 +876,7 @@ define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
|
||||
|
||||
define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
|
||||
ret <4 x i16> %tmp4
|
||||
@ -894,8 +884,7 @@ define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
|
||||
|
||||
define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
|
||||
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
|
||||
ret <8 x i16> %tmp4
|
||||
@ -903,8 +892,7 @@ define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
|
||||
|
||||
define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -912,8 +900,7 @@ define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
|
||||
|
||||
define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -921,8 +908,7 @@ define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
|
||||
|
||||
define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
|
||||
;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1369,8 +1355,7 @@ define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
|
||||
;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp uno <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1382,8 +1367,7 @@ define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
|
||||
;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uno <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1395,8 +1379,7 @@ define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
|
||||
;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uno <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1408,8 +1391,7 @@ define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
|
||||
;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ueq <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1421,8 +1403,7 @@ define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
|
||||
;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ueq <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1434,8 +1415,7 @@ define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
|
||||
;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ueq <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1445,8 +1425,7 @@ define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UGE = ULE with swapped operands, ULE implemented as !OGT.
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp uge <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1456,8 +1435,7 @@ define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UGE = ULE with swapped operands, ULE implemented as !OGT.
|
||||
;CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uge <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1467,8 +1445,7 @@ define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UGE = ULE with swapped operands, ULE implemented as !OGT.
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uge <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1478,8 +1455,7 @@ define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UGT = ULT with swapped operands, ULT implemented as !OGE.
|
||||
;CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ugt <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1489,16 +1465,14 @@ define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UGT = ULT with swapped operands, ULT implemented as !OGE.
|
||||
;CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ugt <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
}
|
||||
define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ugt <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1508,8 +1482,7 @@ define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; ULE implemented as !OGT.
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ule <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1519,8 +1492,7 @@ define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; ULE implemented as !OGT.
|
||||
;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ule <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1529,8 +1501,7 @@ define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; ULE implemented as !OGT.
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ule <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1540,8 +1511,7 @@ define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; ULT implemented as !OGE.
|
||||
;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ult <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1551,8 +1521,7 @@ define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; ULT implemented as !OGE.
|
||||
;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ult <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1561,8 +1530,7 @@ define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; ULT implemented as !OGE.
|
||||
;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ult <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1572,8 +1540,7 @@ define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UNE = !OEQ.
|
||||
;CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp une <2 x float> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1583,8 +1550,7 @@ define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UNE = !OEQ.
|
||||
;CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp une <4 x float> %A, %B
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1593,8 +1559,7 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
|
||||
; Using registers other than v0, v1 are possible, but would be odd.
|
||||
; UNE = !OEQ.
|
||||
;CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp une <2 x double> %A, %B
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1766,8 +1731,7 @@ define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1778,8 +1742,7 @@ define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
|
||||
;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1790,8 +1753,7 @@ define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1800,8 +1762,7 @@ define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
|
||||
define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
|
||||
; UGE with zero = !OLT
|
||||
;CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp uge <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1810,8 +1771,7 @@ define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
|
||||
define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
|
||||
; UGE with zero = !OLT
|
||||
;CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uge <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1819,8 +1779,7 @@ define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
|
||||
define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
|
||||
; UGE with zero = !OLT
|
||||
;CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uge <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1829,8 +1788,7 @@ define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
|
||||
define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
|
||||
; UGT with zero = !OLE
|
||||
;CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1839,8 +1797,7 @@ define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
|
||||
define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
|
||||
; UGT with zero = !OLE
|
||||
;CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1848,8 +1805,7 @@ define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
|
||||
define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
|
||||
; UGT with zero = !OLE
|
||||
;CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1858,8 +1814,7 @@ define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
|
||||
define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
|
||||
; ULT with zero = !OGE
|
||||
;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ult <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1867,8 +1822,7 @@ define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
|
||||
|
||||
define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ult <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1876,8 +1830,7 @@ define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
|
||||
|
||||
define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ult <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1887,8 +1840,7 @@ define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
|
||||
define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
|
||||
; ULE with zero = !OGT
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp ule <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1897,8 +1849,7 @@ define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
|
||||
define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
|
||||
; ULE with zero = !OGT
|
||||
;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ule <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1907,8 +1858,7 @@ define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
|
||||
define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
|
||||
; ULE with zero = !OGT
|
||||
;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp ule <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1917,8 +1867,7 @@ define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
|
||||
define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
|
||||
; UNE with zero = !OEQ with zero
|
||||
;CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp une <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1927,8 +1876,7 @@ define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
|
||||
define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
|
||||
; UNE with zero = !OEQ with zero
|
||||
;CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp une <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1936,8 +1884,7 @@ define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
|
||||
define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
|
||||
; UNE with zero = !OEQ with zero
|
||||
;CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp une <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
@ -1949,8 +1896,7 @@ define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
||||
%tmp3 = fcmp uno <2 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
|
||||
ret <2 x i32> %tmp4
|
||||
@ -1961,8 +1907,7 @@ define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uno <4 x float> %A, zeroinitializer
|
||||
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
|
||||
ret <4 x i32> %tmp4
|
||||
@ -1973,8 +1918,7 @@ define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
|
||||
;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
|
||||
;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
|
||||
;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
|
||||
%tmp3 = fcmp uno <2 x double> %A, zeroinitializer
|
||||
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
|
||||
ret <2 x i64> %tmp4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user