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https://github.com/RPCS3/llvm-mirror.git
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Assorted fixes:
* Stop being pessimistic about output register allocation * Start to handle function descriptors: compute target GPs and so on when doing indirect calls etc. Not there yet, though. For the moment, we try to use _indirect_ branches wherever possible, to stress test function descriptors. * FP divide-by-zero should work now * add varargs (it doesn't work, though) At this point, all of SingleSource passes (modulo C++ tests that are due to issues with the CFE, see note in the README.) Much of MultiSource also passes although there's still a ton of bugs around. Something for me to work on tomorrow, then. :) llvm-svn: 20960
This commit is contained in:
Duraid Madina
parent
f2d1865c74
commit
47fed18416
@ -118,6 +118,12 @@ namespace {
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BuildMI(BB, IA64::MOV, 1, IA64::rp).addReg(RP);
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}
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void restoreSP_RP(MachineBasicBlock* BB)
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{
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BuildMI(BB, IA64::MOV, 1, IA64::r12).addReg(SP);
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BuildMI(BB, IA64::MOV, 1, IA64::rp).addReg(RP);
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}
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void restoreRP(MachineBasicBlock* BB)
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{
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BuildMI(BB, IA64::MOV, 1, IA64::rp).addReg(RP);
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@ -161,7 +167,9 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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unsigned used_FPArgs = 0; // how many FP args have been used so far?
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unsigned ArgOffset = 0;
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int count = 0;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
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{
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SDOperand newroot, argt;
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@ -206,7 +214,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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}
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} else { // more than 8 args go into the frame
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(8, 16 + 8 * (count - 8));
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ArgOffset = 16 + 8 * (count - 8);
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int FI = MFI->CreateFixedObject(8, ArgOffset);
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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@ -219,6 +228,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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ArgValues.push_back(argt);
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}
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// Create a vreg to hold the output of (what will become)
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// the "alloc" instruction
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VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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@ -239,8 +249,27 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
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// ..hmm.
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unsigned tempOffset=0;
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// if this is a varargs function, we simply lower llvm.va_start by
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// pointing to the first entry
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if(F.isVarArg()) {
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tempOffset=0;
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VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
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}
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// here we actually do the moving of args, and store them to the stack
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// too if this is a varargs function:
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for (int i = 0; i < count && i < 8; ++i) {
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BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
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if(F.isVarArg()) {
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// if this is a varargs function, we copy the input registers to the stack
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int FI = MFI->CreateFixedObject(8, tempOffset);
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tempOffset+=8; //XXX: is it safe to use r22 like this?
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BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
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// FIXME: we should use st8.spill here, one day
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BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
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}
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}
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return ArgValues;
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@ -253,15 +282,22 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
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MachineFunction &MF = DAG.getMachineFunction();
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// fow now, we are overly-conservative and pretend that all 8
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// outgoing registers (out0-out7) are always used. FIXME
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// update comment line 137 of MachineFunction.h
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MF.getInfo<IA64FunctionInfo>()->outRegsUsed=8;
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unsigned NumBytes = 16;
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if (Args.size() > 8)
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unsigned outRegsUsed = 0;
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if (Args.size() > 8) {
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NumBytes += (Args.size() - 8) * 8;
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outRegsUsed = 8;
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} else {
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outRegsUsed = Args.size();
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}
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// FIXME? this WILL fail if we ever try to pass around an arg that
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// consumes more than a single output slot (a 'real' double, int128
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// some sort of aggregate etc.), as we'll underestimate how many 'outX'
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// registers we use. Hopefully, the assembler will notice.
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MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
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std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
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Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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@ -318,10 +354,24 @@ std::pair<SDOperand,SDOperand> IA64TargetLowering::
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LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
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const Type *ArgTy, SelectionDAG &DAG) {
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assert(0 && "LowerVAArgNext not done yet!\n");
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abort();
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MVT::ValueType ArgVT = getValueType(ArgTy);
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SDOperand Result;
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if (!isVANext) {
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Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
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} else {
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unsigned Amt;
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if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
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Amt = 8;
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else {
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assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
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"Other types should have been promoted for varargs!");
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Amt = 8;
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}
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Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
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DAG.getConstant(Amt, VAList.getValueType()));
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}
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return std::make_pair(Result, Chain);
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}
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std::pair<SDOperand, SDOperand> IA64TargetLowering::
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LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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@ -470,6 +520,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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abort();
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}
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/*
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Select(N.getOperand(0));
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if (ConstantSDNode* CN = dyn_cast<ConstantSDNode>(N.getOperand(1)))
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{
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@ -487,7 +538,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI(BB, IA64::SUB, 2, IA64::r12).addReg(IA64::r12).addReg(Tmp1);
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}
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*/
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI(BB, IA64::SUB, 2, IA64::r12).addReg(IA64::r12).addReg(Tmp1);
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// Put a pointer to the space into the result register, by copying the
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// stack pointer.
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BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r12);
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@ -569,16 +624,17 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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unsigned Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, IA64::ADD, 2, Tmp1).addGlobalAddress(GV).addReg(IA64::r1);
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//r1==GP
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BuildMI(BB, IA64::LD8, 1, Result).addReg(Tmp1);
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return Result;
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}
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case ISD::ExternalSymbol: {
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const char *Sym = cast<ExternalSymbolSDNode>(N)->getSymbol();
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assert(0 && "ISD::ExternalSymbol not done yet\n");
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//XXX BuildMI(BB, IA64::MOV, 1, Result).addExternalSymbol(Sym);
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// assert(0 && "sorry, but what did you want an ExternalSymbol for again?");
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BuildMI(BB, IA64::MOV, 1, Result).addExternalSymbol(Sym); // XXX
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return Result;
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}
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@ -944,7 +1000,8 @@ pC = pA OR pB
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case ISD::UREM: isModulus=true; isSigned=false; break;
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}
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unsigned TmpPR=MakeReg(MVT::i1); // we need a scratch predicate register,
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unsigned TmpPR=MakeReg(MVT::i1); // we need two scratch
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unsigned TmpPR2=MakeReg(MVT::i1); // predicate registers,
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unsigned TmpF1=MakeReg(MVT::f64); // and one metric truckload of FP regs.
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unsigned TmpF2=MakeReg(MVT::f64); // lucky we have IA64?
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unsigned TmpF3=MakeReg(MVT::f64); // well, the real FIXME is to have
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@ -989,6 +1046,14 @@ pC = pA OR pB
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BuildMI(BB, IA64::FRCPAS1FLOAT, 2, TmpF5).addReg(TmpF3).addReg(TmpF4);
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BuildMI(BB, IA64::FRCPAS1PREDICATE, 2, TmpPR).addReg(TmpF3).addReg(TmpF4);
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if(!isModulus) { // if this is a divide, we worry about div-by-zero
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unsigned bogusPR=MakeReg(MVT::i1); // won't appear, due to twoAddress
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// TPCMPNE below
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BuildMI(BB, IA64::CMPEQ, 2, bogusPR).addReg(IA64::r0).addReg(IA64::r0);
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BuildMI(BB, IA64::TPCMPNE, 3, TmpPR2).addReg(bogusPR)
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.addReg(IA64::r0).addReg(IA64::r0).addReg(TmpPR);
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}
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// now we apply newton's method, thrice! (FIXME: this is ~72 bits of
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// precision, don't need this much for f32/i32)
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BuildMI(BB, IA64::CFNMAS1, 4, TmpF6)
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@ -1023,8 +1088,16 @@ pC = pA OR pB
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}
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if(!isModulus) {
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if(isFP)
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BuildMI(BB, IA64::FMOV, 1, Result).addReg(TmpF15);
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if(isFP) { // extra worrying about div-by-zero
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unsigned bogoResult=MakeReg(MVT::f64);
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// we do a 'conditional fmov' (of the correct result, depending
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// on how the frcpa predicate turned out)
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BuildMI(BB, IA64::PFMOV, 2, bogoResult)
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.addReg(TmpF12).addReg(TmpPR2);
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BuildMI(BB, IA64::CFMOV, 2, Result)
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.addReg(bogoResult).addReg(TmpF15).addReg(TmpPR);
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}
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else
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BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TmpF15);
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} else { // this is a modulus
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@ -1329,6 +1402,7 @@ pC = pA OR pB
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case MVT::f64:
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BuildMI(BB, IA64::FMOV, 1, FPArgs[used_FPArgs++])
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.addReg(argvregs[i]);
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// FIXME: we don't need to do this _all_ the time:
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BuildMI(BB, IA64::GETFD, 1, intArgs[i]).addReg(argvregs[i]);
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break;
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}
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@ -1363,6 +1437,9 @@ pC = pA OR pB
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break;
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}
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}
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/* XXX we want to re-enable direct branches! crippling them now
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* to stress-test indirect branches.:
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//build the right kind of call
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(1)))
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@ -1370,22 +1447,42 @@ pC = pA OR pB
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BuildMI(BB, IA64::BRCALL, 1).addGlobalAddress(GASD->getGlobal(),true);
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IA64Lowering.restoreGP_SP_RP(BB);
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}
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else if (ExternalSymbolSDNode *ESSDN =
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^^^^^^^^^^^^^ we want this code one day XXX */
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if (ExternalSymbolSDNode *ESSDN =
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
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{
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BuildMI(BB, IA64::BRCALL, 0)
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{ // FIXME : currently need this case for correctness, to avoid
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// "non-pic code with imm relocation against dynamic symbol" errors
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BuildMI(BB, IA64::BRCALL, 1)
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.addExternalSymbol(ESSDN->getSymbol(), true);
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IA64Lowering.restoreGP_SP_RP(BB);
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}
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else {
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// no need to restore GP as we are doing an indirect call
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Tmp1 = SelectExpr(N.getOperand(1));
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// b6 is a scratch branch register, we load the target:
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BuildMI(BB, IA64::MOV, 1, IA64::B6).addReg(Tmp1);
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unsigned targetEntryPoint=MakeReg(MVT::i64);
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unsigned targetGPAddr=MakeReg(MVT::i64);
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unsigned currentGP=MakeReg(MVT::i64);
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// b6 is a scratch branch register, we load the target entry point
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// from the base of the function descriptor
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BuildMI(BB, IA64::LD8, 1, targetEntryPoint).addReg(Tmp1);
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BuildMI(BB, IA64::MOV, 1, IA64::B6).addReg(targetEntryPoint);
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// save the current GP:
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BuildMI(BB, IA64::MOV, 1, currentGP).addReg(IA64::r1);
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/* TODO: we need to make sure doing this never, ever loads a
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* bogus value into r1 (GP). */
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// load the target GP (which is at mem[functiondescriptor+8])
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BuildMI(BB, IA64::ADDIMM22, 2, targetGPAddr)
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.addReg(Tmp1).addImm(8); // FIXME: addimm22? why not postincrement ld
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BuildMI(BB, IA64::LD8, 1, IA64::r1).addReg(targetGPAddr);
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// and then jump: (well, call)
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BuildMI(BB, IA64::BRCALL, 1).addReg(IA64::B6);
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IA64Lowering.restoreGP_SP_RP(BB);
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// and finally restore the old GP
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BuildMI(BB, IA64::MOV, 1, IA64::r1).addReg(currentGP);
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IA64Lowering.restoreSP_RP(BB);
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}
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switch (Node->getValueType(0)) {
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@ -77,7 +77,9 @@ INFO:
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KNOWN DEFECTS AT THE CURRENT TIME:
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- no varargs
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- C++ vtables contain naked function pointers, not function descriptors,
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which is bad. see http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=406
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- varargs are broken
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- alloca doesn't work (indeed, stack frame layout is bogus)
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- no support for big-endian environments
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- (not really the backend, but...) the CFE has some issues on IA64.
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